Week In Review: Design, Low Power

DisplayPort 2.0 spec & VIP; OpenCAPI VIP; early RTL verification.


VESA published the DisplayPort 2.0 standard, which allows for a max payload of 77.37 Gbps, a 3X increase in data bandwidth performance compared to DisplayPort 1.4a. The latest release also includes capabilities to address beyond 8K resolutions, higher refresh rates and HDR support at higher resolutions, multiple display configurations, and support for 4K-and-beyond VR resolutions. It is backwards compatible and incorporates all of the key features of DP 1.4a such as visually lossless Display Stream Compression and HDR metadata transport. DP 2.0 uses the Thunderbolt 3 PHY layer and includes a display stream data mapping protocol common to both single-stream transport and multi-stream transport.

Cadence unveiled Verification IP for the new DisplayPort 2.0 standard. The VIP provides comprehensive protocol validation solution for DisplayPort designs and includes a configurable bus functional model (BFM), a protocol monitor and a library of integrated protocol checks to optimize verification predictability. Additionally, the VIP has been designed for easy integration into testbenches at IP, SoC and system levels.

SmartDV debuted Verification IP to support the OpenCAPI standard. OpenCAPI is aimed at boosting the performance of data center servers tasked with analyzing large amounts of data. The VIP verifies OpenCAPI interfaces and includes an extensive test suite that performs random or directed protocol tests to create a range of scenarios to effectively verify the design under test and is compatible with 3.0 and 3.1 releases. The VIP is supported for all major verification languages and methodologies including OVM, UVM, and SystemC.

Real Intent improved its Ascent AutoFormal automatic RTL verification tool, providing 5-10x speedup of the tool’s single core engine plus a 2-4X speedup from the automatic splitting of runs across parallel cores as well as the ability to analyze 5X larger designs when compared to the previous version. The new engines dynamically determine whether or not the analysis is converging for a particular check and move on to a new check when necessary.

Synopsys announced Virtualizer Development Kits (VDKs) for Infineon’s third-generation AURIX microcontroller family for automotive, providing a way for Infineon customers to develop software, perform regression testing, and fault injection before silicon availability. VDKs for AURIX TC2x and TC3x series are available now, while one for AURIX TC4x series is planned to be available in Q1 2020.

Rambus expanded its CryptoManager Root of Trust family of programmable, hardware-level secure silicon IP cores. Application-targeted cores include the RT-730 for automotive designs with an ISO-26262-2018 ASIL-D-ready implementation; the RT-630 for cloud, AI and ML accelerator chips; and the RT-650 and RT-660 for government-focused chip designs needing FIPS 140-2 Cryptographic Module Validation Program (CMVP) certification.

ANSYS’ autonomous vehicle simulator VRXPERIENCE now includes AVSimulation’s SCANeR Studio product as its driving simulator module. VRXPERIENCE includes HMI testing, physical sensor simulation, embedded software controls integration, headlamp simulation and links to simulation data management and systems safety analysis. SCANeR Studio incorporates roads generated from high definition maps and asset libraries, traffic situations, weather conditions, and vehicle dynamics.

Iluvatar CoreX selected Mentor’s Veloce Strato emulation platform for the verification of its AI cloud training SoC chipset and proprietary software platform. Iluvatar CoreX noted that Mentor’s virtual solutions, such as VirtuaLab PCIe and Protocol Analyzer, were a vital element of the verification environment.

NanoSemi deployed OneSpin’s formal verification solution 360 DV-Verify with the SystemC/C++ extension for verification of its machine learning-based IP for 5G and Wi-Fi applications. NanoSemi cited the ability to support FPGA and SoC flows and perform exhaustive verification without complicating debug efforts.

Uhnder included Arteris IP’s FlexNoC IP as the on-chip interconnect for its new automotive radar-on-chip (RoC). Uhnder cited the extent of on-chip integration and meeting the product’s huge bandwidth requirements while avoiding routing congestion.

UltraSoC closed a £5 million (~$6.3m) equity funding round. eCAPITAL and Seraphim Capital joined existing investors Indaco Venture Partners, Octopus Ventures, Oxford Capital, Techgate, and business angel Guillaume d’Eyssautier. The funds will be used to recruit hardware and software engineers at its headquarters in Cambridge, UK, and design center in Bristol UK. UltraSoC also plans to open an engineering center in Warsaw, Poland to develop its data science and machine-learning technologies.

Synopsys achieved 2019 CarbonNeutral certification across its global operations, including offices, data centers, business travel, and employee commute, offsetting approximately 100,000 metric tons of carbon dioxide equivalent through the purchase of Renewable Energy Certificates (RECs) and investments in offset projects. “Being an industry leader means that we not only deliver the most advanced technology for silicon chip design and verification, IP integration, and application security testing, but also take responsibility for the carbon emissions resulting from our environmental footprint,” said Synopsys co-CEO Aart de Geus. “Climate change is one of the most pressing global challenges of our time, and it can only be solved through the efforts of every government, business organization, and individual.”

ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West.

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