tag: formal

EDA Grabs Bigger Slice Of Chip Market
By Brian Bailey - 31 Jan, 2019 - Comments: 0

EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Taming Concurrency
By Brian Bailey - 17 Jan, 2019 - Comments: 2

Concurrency adds complexity for which the industry lacks appropriate tools, and the problem has grown to the point where errors can creep into designs with no easy or consistent way to detect them. In the past, when chips were essentially a single pipeline, this wasn't a problem. In fact, the early pioneers of EDA created a suitable language to describe and contain the necessary concurrency ... » read more

The Fibonacci Calculator
By Sergio Marchese - 20 Dec, 2018 - Comments: 0

The holiday season is all about traditions, and the annual holiday puzzle has become a tradition here at OneSpin. Two years ago, we challenged engineers everywhere to solve the famous Einstein’s Riddle using a formal tool. We received some interesting solutions. Last year, we drew an even bigger response to our invitation to tackle the “World’s Hardest Sudoku.” These puzzles are fun, of... » read more

Week In Review: Design, Low Power
By Jesse Allen - 30 Nov, 2018 - Comments: 0

Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

Heterogeneous Computing Raises The Bar For Functional Verification
By Raik Brinkmann - 29 Nov, 2018 - Comments: 0

If there’s one thing certain in chip development, it’s that every innovation in architecture or semiconductor technology puts more pressure on the functional verification process. The increase in gate count for each new technology node stresses tool capacity. Every step up in complexity makes it harder to find deep, corner-case bugs. The dramatic growth in SoC designs brings software into p... » read more

Blog Review: Nov. 14
By Jesse Allen - 14 Nov, 2018 - Comments: 0

Mentor's Jin Hou and Joe Hupcey III explain two fundamental characteristics of formal analysis that simplify things for the formal algorithm and provide better wall clock run time and memory usage performance. Cadence's Paul McLellan shares highlights from five presentations all discussing what's behind AI's movement to edge devices, the vast amount of investment going into the area, and whe... » read more

The Impact of Domain Crossing on Safety
By Brian Bailey - 31 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Oct, 2018 - Comments: 0

Tools OneSpin launched a formal verification tool that integrates with all major simulators, coverage databases and viewers, and chip design verification planning tools to provide a comprehensive view of verification progress. Comprised of two new formal apps, it can identify unreachable coverage points and provide them to the simulator to reduce wasted effort. Synopsys released the latest ... » read more

Integrating Results And Coverage From Simulation And Formal
By Tom Anderson - 25 Oct, 2018 - Comments: 0

Not so long ago, formal verification was considered an exotic technology used only by specialists for specific verification challenges such as cache coherency. As chips have grown ceaselessly in size and complexity, the traditional verification method of simulation could not keep pace. The task of generating and running enough tests consumed enormous resources in terms of engineers, simulation ... » read more

AI Chips Must Get The Floating-Point Math Right
By Sergio Marchese - 27 Sep, 2018 - Comments: 0

Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks today are often based on operations that use multiplication and addition of floating-point values, which subsequently need to be scaled to different sizes and for different needs. Modern FPGAs such as Intel Arria-10 ... » read more

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