tag: formal

Shhhhh… Deadlocks Anonymous In Session
By Rajesh Ramanujam - 26 Oct, 2017 - Comments: 0

I am sure there is an anonymous group – like Alcoholics Anonymous – headquartered in Silicon Valley, meeting every quarter to discuss the deadlocks that have paralyzed their products, roadmap and deployments. In discreet venues in every town, small groups of engineers huddle together to share war stories about the disgruntled customers whose trust was lost because of a deadlock discovered o... » read more

DVCon Europe Takes Over Munich October 16-17
By McKenzie Ross - 28 Sep, 2017 - Comments: 0

DVCon Europe is on the horizon, and this year's program should prove to be very timely. Chips and systems are getting more complex, verification is becoming more difficult, and formal has emerged as a critical piece of the verification suite The lineup this year tackles some key issues facing a changing semiconductor landscape. During a Monday tutorial, “Next Generation ISO 26262-based De... » read more

When Is Verification Complete?
By Ann Mutschler - 24 Aug, 2017 - Comments: 0

Deciding when verification is done is becoming a much more difficult decision, prompting verification teams to increasingly rely on metrics rather than just the tests listed in the verification plan. This trend has been underway for the past couple of process nodes, but it takes time to spot trends and determine whether they are real or just aberrations. The Wilson Research Group conducts a ... » read more

And The Winners Are… 10 Formal Solutions To Einstein’s Riddle
By Sergio Marchese - 27 Jul, 2017 - Comments: 5

A few months back, OneSpin asked engineers to solve the classic Einstein’s Riddle using a formal tool. The challenge became hugely popular, and we received many outstanding solutions. To check out the riddle itself and the top 10 solutions created by leading engineers, click here. In this blog, we take another look at the riddle, review the best solutions and announce the winners. We ha... » read more

The Safe Road Trip Thanks To Formal Verification
By Dave Kelf - 29 Jun, 2017 - Comments: 0

School’s out, gas is cheap and families in the U.S. are piling into their cars or minivans to take the time-honored cross-country road trip. These days, kids in the backseat don’t need to entertain themselves by spotting the license plates from the 50 U.S. states or picking a fight with their brother or sister. Instead, they can be kept amused with the vehicle’s sophisticated entertainmen... » read more

Formal Verification’s Continental Divide
By Dave Kelf - 25 May, 2017 - Comments: 0

Formal verification is picking up steam with engineering groups worldwide doing complex functional verification for bug-free and reliable digital chips. In fact, many difficult verification challenges are solved with formal verification, given its flexibility in targeting a broad range of verification challenges. Recent advances in formal verification’s ease of use and capacity has made it an... » read more

Can Formal Replace Simulation?
By Brian Bailey - 01 May, 2017 - Comments: 1

A year ago, [getentity id="22147" comment="Oski Technology"] achieved something that had never happened before. It brought together 15 of the top minds in [getkc id="33" kc_name="formal verification"] deployment and sat them down in a room to discuss the problems and issues they face and the ways in which they are attempting to solve those problems. Semiconductor Engineering was there to record... » read more

Rediscovering Coverage Insurance
By Dave Kelf - 27 Apr, 2017 - Comments: 0

When coverage comes up in conversation, if it comes up at all, it’s always a matter of car, home or health insurance. Coverage and functional verification are unlikely to be used in that discussion, or any other for that matter. That’s too bad because engineering groups grapple with when is enough verification enough, like some kind of coverage insurance. Oh sure, simulation and emulatio... » read more

10 Ways To Skin A Formal Puzzle
By Dave Kelf - 23 Mar, 2017 - Comments: 1

During the holidays, OneSpin issued a challenge to solve the classic Einstein’s Riddle using any formal verification tool. Although this puzzle was meant to be a little holiday fun, its solution required thought and some useful formal techniques applicable in everyday functional verification. We received a broad range of answers from engineers across the globe in different companies, inclu... » read more

Carving Up Verification
By Ed Sperling - 23 Mar, 2017 - Comments: 0

Anirudh Devgan, executive vice president and general manager of [getentity id="22032" e_name="Cadence's"] System & Verification Group, sat down with Semiconductor Engineering to discuss the evolution of verification. What follows are excerpts of that conversation. SE: What’s changing in [getkc id="10" kc_name="verification"]? Devgan: Parallelism, greater capacity and multiple engine... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy