tag: foundries

Implementing High-Density-Advanced Packaging for OSATs And Foundries
By Mentor, a Siemens Business - 12 Jul, 2017 - Comments: 0

HDAP design and verification require cooperation and collaboration between design houses, OSATs, foundries, and EDA vendors. By using common tools that have the integration and functionality needed to operate in both the IC and packaging domains and by developing and deploying process optimized design-kits such as ADK’s and PDKs, OSATs, foundries, and their customers can achieve design, fabri... » read more

Implementing High-Density-Advanced Packaging For OSATs And Foundries
By Mentor, a Siemens Business - 05 Jun, 2017 - Comments: 0

HDAP design and verification require cooperation and collaboration between design houses, OSATs, foundries, and EDA vendors. By using common tools that have the integration and functionality needed to operate in both the IC and packaging domains and by developing and deploying process optimized design-kits such as ADK’s and PDKs, OSATs, foundries, and their customers can achieve design, fabri... » read more

Foundry Wars, Take Two
By Ed Sperling - 25 May, 2017 - Comments: 0

Samsung, GlobalFoundries, TSMC and Intel all have declared their intention to fill in nearly every node possible with multiple processes, different packaging options, and new materials. In fact, the only number that hasn't been taken so far is 9nm. It's not that one foundry's 10nm is the same as another's. Each company defines its nodes differently, and these days comparing nodes is almost m... » read more

Samsung Unveils Scaling, Packaging Roadmaps
By Ed Sperling - 24 May, 2017 - Comments: 5

Samsung Foundry unveiled an aggressive roadmap that scales down to 4nm, and which includes a fan-out wafer-level packaging technology that bridges chips in the redistribution layer, 18nm FD-SOI, and a new organizational structure that allows the unit much greater autonomy as a commercial enterprise. The moves put [getentity id="22865" e_name="Samsung Foundry"] in direct competition with [get... » read more

2.5D Adds Test Challenges
By Jeff Dorsch - 06 Mar, 2017 - Comments: 0

OSATs and ATE vendors are making progress in determining what works and what doesn't in 2.5D packaging, expanding their knowledge base as this evolves into a mainstream technology. A [getkc id="82" kc_name="2.5D"] package generally includes an ASIC connected to a stack of memory chips—usually high-bandwidth memory—using an [getkc id="204" kc_name="interposer"] or some type of silicon bri... » read more

Deeper Inside Intel
By Mark LaPedus - 22 Aug, 2016 - Comments: 5

Mark Bohr, senior fellow and director of process architecture and integration at Intel, and Zane Ball, vice president in the Technology and Manufacturing Group at Intel and co-general manager of Intel Custom Foundry, sat down with Semiconductor Engineering to discuss the future directions of transistors, process technology, the foundry business and packaging. What follows are excerpts of those ... » read more

Changing Economics In Chip Manufacturing
By Ed Sperling - 18 Aug, 2016 - Comments: 1

The foundry and equipment businesses are poised for significant changes that could affect the balance of power far beyond just the semiconductor manufacturing sector. It’s no secret that the number of companies developing new chips at 7nm is shrinking. There will be even fewer at 5nm. The business case for moving forward is that density must provide a competitive edge. But that density imp... » read more

Foundry Capacity Investment Led By Taiwan And China
By Clark Tseng - 21 Jul, 2016 - Comments: 0

The era of every company building a captive fab for next-generation products is ancient history, as foundries throughout the world provide leading-edge technology and flexible capacity in a timely and cost-effective manner. In today’s mobile-driven ecosystem, faster product development cycles and time-to-market have become the norm for the industry. Now, this trend is even spreading to the co... » read more

The Other Side Of Device Scaling
By Ed Sperling - 19 May, 2016 - Comments: 0

The push to 10nm and 7nm is a relatively straightforward path in PowerPoint. In multiple presentations across the semiconductor industry, in fact, it has been portrayed as a straight line progression spanning decades. While most chipmakers are aware that the cost per transistor has been increasing below 22nm, due to double patterning and the challenges in designing finFETs and dealing with d... » read more

IP Business Models In Flux
By Ann Mutschler - 12 May, 2016 - Comments: 0

EDA and IP suppliers are engaging with foundries earlier with each manufacturing process node, while those foundries are providing ever more optimized and tuned processes to their customers. As part of this, IP providers must port their IP offerings to the various foundries and processes, putting a squeeze on resources. That raises some difficult questions, such as how to prioritize their li... » read more

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