tag: FPGA

FPGAs Drive Deeper Into Cars
By Ann Mutschler - 09 Jul, 2018 - Comments: 3

FPGAs are reaching deeper and wider inside of automobiles, playing an increasingly important role across more systems within a vehicle as the electronic content continues to grow. The role of FPGAs in automotive cameras and sensors is already well established. But they also are winning sockets inside of a raft of new technologies, ranging from the AI systems that will become the central logi... » read more

Embedded FPGA Design Considerations
By Ed Sperling - 09 Jul, 2018 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about interconnects, memory, different design approaches, and why foundry processes are critical to eFPGA design. https://youtu.be/FngrgDnJn9c » read more

SoC FPGAs And HW/SW Co-Simulation
By Farhad Fallahlalehzari - 28 Jun, 2018 - Comments: 0

Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing system (PS) with state-of-the-art programmable logic (PL). This combination allows a system to be architected to provide an optimally balanced single-chip software/hardware solution. However, all too often, the integration between the PS and PL takes place late... » read more

FPGAs Becoming More SoC-Like
By Ann Mutschler - 04 Jun, 2018 - Comments: 1

FPGAs are blinged-out rockstars compared to their former selves. No longer just a collection of look-up tables (LUTs) and registers, FPGAs have moved well beyond into now being architectures for system exploration and vehicles for proving a design architecture for future ASICs. This family of devices now includes everything from basic programmable logic all the way up to complex SoC devices.... » read more

Higher Performance, Lower Power Everywhere
By Ed Sperling - 10 May, 2018 - Comments: 0

The future of technology is all about information—not just data—at our fingertips, anywhere and at any time. But making all of this work properly will require massive improvements in both performance and power efficiency. There are several distinct pieces to this picture. One is architectural, which is possibly the simplest to understand, the most technologically challenging to realize, ... » read more

Understanding NI CompactRIO Scan Mode
By NI - 07 May, 2018 - Comments: 0

The LabVIEW Real-Time Module 8.6 introduced powerful new features for programming CompactRIO hardware that reduce development time and complexity as well as provide tools for monitoring and maintaining CompactRIO applications. This functionality is powered by two technologies in LabVIEW, the NI Scan Engine and the RIO Scan Interface. The NI Scan Engine is a new component of LabVIEW Real-Time th... » read more

Inside UVM, Take Three
By Vatsal Choksi - 26 Apr, 2018 - Comments: 0

The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking block or run phases. Now, it is very important that the time at which test vectors applied from test-bench reaches the Design Under Test(DUT) at the same time. If timing for different signals vari... » read more

Why Your FPGA Synthesis Flow Requires Verification
By Tom Anderson - 26 Apr, 2018 - Comments: 0

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL language that looks more like software than hardware, and implements it using the low-level building-block library of an ASIC or FPGA device. The resulting gate-level netlist must meet a variety of requir... » read more

Tech Talk: FPGA RTL Checking
By Ed Sperling - 26 Apr, 2018 - Comments: 3

Tobias Welp, software architect and engineering manager at OneSpin Solutions, explains how to ensure the RTL created by design engineers matches what shows up in an FPGA. https://youtu.be/0N1PDYyq0dY » read more

New Market Drivers
By Brian Bailey - 25 Apr, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss changing market dynamics with Steve Mensor, vice president of marketing for [getentity id="22926" e_name="Achronix"]; Apurva Kalia, vice president of R&D in the System and Verification group of [getentity id="22032" e_name="Cadence"]; Mohammed Kassem, CTO for [getentity id="22910" comment="efabless"]; Matthew Ballance, product engineer and techn... » read more

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