tag: Fraunhofer IESE

Chip Industry Technical Paper Roundup: April 30
By Linda Christensen - 30 Apr, 2024 - Comments: 0

These new technical papers were recently added to Semiconductor Engineering’s library. [table id=222 /] Find more technical papers here. » read more

Feasibility and Potential of Quantum Computing For a Typical EDA Optimization Problem
By Technical Paper Link - 16 Apr, 2024 - Comments: 0

A new technical paper titled "QCEDA: Using Quantum Computers for EDA" was published by researchers at Fraunhofer IESE, RPTU Kaiserslautern, DLR (Germany), and OTH Regensburg. Abstract "The field of Electronic Design Automation (EDA) is crucial for microelectronics, but the increasing complexity of Integrated Circuits (ICs) poses challenges for conventional EDA: Corresponding problems are of... » read more

Chip Industry Week In Review
By The SE Staff - 20 Oct, 2023 - Comments: 0

By Susan Rambo, Gregory Haley, and Liz Allan SRC unfurled its Microelectronics and Advanced Packaging (MAPT) industry-wide 3D semiconductor roadmap, addressing such topics as advanced packaging, heterogeneous integration, analog and mixed-signal semiconductors, energy efficiency, security, the related foundational ecosystem, and more. The guidance is the collective effort of 300 individuals ... » read more

Using Run-Time Reverse-Engineering to Optimize DRAM Refresh
By Technical Paper Link - 31 Dec, 2017 - Comments: 0

Abstract: "The overhead of DRAM refresh is increasing with each density generation. To help offset some of this overhead, JEDEC designed the modern Auto-Refresh command with a highly optimized architecture internal to the DRAM---an architecture that violates the timing rules external controllers must observe and obey during normal operation. Numerous refresh-reduction schemes manually refresh ... » read more

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