tag: Fraunhofer IIS EAS

Designing For Ultra-Low-Power IoT Devices
By Ann Mutschler - 19 Dec, 2018 - Comments: 1

Optimizing designs for power is becoming the top design challenge in battery-driven IoT devices, boxed in by a combination of requirements such as low cost, minimum performance and functionality, as well as the need for at least some of the circuits to be always on. Power optimization is growing even more complicated as AI inferencing moves from the data center to the edge. Even simple... » read more

The Cost Of Accuracy
By Brian Bailey - 13 Dec, 2018 - Comments: 0

How accurate does a system need to be, and what are you willing to pay for that accuracy? There are many sources of inaccuracy throughout the development flow of electronic systems, most of which involve complex tradeoffs. Inaccuracy leaves an impact on your design in ways you are not even aware of, hidden by best practices or guard-banding. EDA tools also inject some inaccuracy. As the i... » read more

Ultra-Low-Power SAR ADC in 22 nm FD-SOI Technology Using Body-Biasing
By Fraunhofer IIS/EAS - 12 Dec, 2018 - Comments: 0

Today’s sensor applications show a rising demand on miniaturized autonomous sensors nodes with extreme requirements on power dissipation. One core functionality of these sensor nodes is the conversion of analog sensor signals to digital data for post processing and data communication. In this work a 11-bit Successive Approximation Register (SAR) ADC with minimized power dissipation is develop... » read more

How To Improve Analog Design Reuse
By Ann Mutschler - 14 Nov, 2018 - Comments: 0

Digital circuit design is largely automated today, but most analog components still are designed manually. This may change soon. As analog design grows increasingly complex and error-prone, design teams and tool vendors are focusing on how to automate as much of the design of analog circuits as possible. Analog design is notoriously difficult and varied. It can include anything from power ma... » read more

Interaction Of Hard IP And Chip-Package
By Andy Heinig - 08 Nov, 2018 - Comments: 0

Current and future customer-specific circuit development requires an increasing number of different interfaces, such as for memory (DDR3, DDR4, LPDDR3, LPDDR4, etc.), radio interfaces (Bluetooth, NBIoT, etc.) or high-speed LVDS/SERDES interfaces (DisplayPort, Ethernet, USB, etc.). For customer-specific circuit projects, these components are frequently purchased as hard IP because the developmen... » read more

Taming NBTI To Improve Device Reliability
By Ann Mutschler - 08 Nov, 2018 - Comments: 2

Negative-bias temperature instability is a growing issue at the most advanced process nodes, but it also has proven extremely difficult to tame using conventional approaches. That finally may be starting to change. NBTI is an aging mechanism in field-effect transistors that leads to a change of the characteristic curves of a transistor during operation. The result can be a drift toward unint... » read more

Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh Environments
By Fraunhofer IIS/EAS - 07 Nov, 2018 - Comments: 0

On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is able to predict the bit failures caused by the stress via the piezoresistive effect. The stability of each single SRAM cell is simulated using static noise margin. Finally, the whole array’s behavio... » read more

Carmakers To Chipmakers: Where’s The Data?
By SE Staff - 24 Oct, 2018 - Comments: 0

The integration of electronics into increasingly autonomous vehicles isn't going nearly as smoothly as the marketing literature suggests. In fact, it could take years before some of these discrepancies are resolved. The push toward full autonomy certainly hasn't slowed down, but carmakers and the electronics industry are approaching that goal from very different vantage points. Carmakers and... » read more

Functional Safety And Requirements Engineering
By Roland Jancke - 11 Oct, 2018 - Comments: 0

Currently, dramatically increasing design costs are being reported for safety-critical applications. This is caused by additional necessary actions to implement and verify functional safety requirements. Such requirements are appearing with a clearly increasing tendency in the area of mobility (automotive, transport, aerospace) as well as in industrial automation and medical technology. In many... » read more

Power Delivery Affecting Performance At 7nm
By Brian Bailey - 11 Oct, 2018 - Comments: 4

Complex interactions and dependencies at 7nm and beyond can create unexpected performance drops in chips that cannot always be caught by signoff tools. This isn't for lack of effort. The amount of time spent trying to determine if an advanced-node chip will work after it is fabricated has been rising steadily for several process nodes. Additional design rules handle everything from variation... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy