Low-Power Design Becomes Even More Complex

New markets, technologies and tradeoffs that span multiple different disciplines are turning this into an increasingly difficult team effort.


Throughout the SoC design flow, there has been a tremendous amount of research done to ease the pain of managing a long list of power-related issues. And while headway has been made, the addition of new application areas such as AI/ML/DL, automotive and IoT has raised as many new problems as have been solved.

The challenges are particularly acute at leading-edge nodes where devices are powered by a battery. That includes a long list of factors, starting with the most suitable semiconductor technology, according Torsten Reich, group manager Integrated Sensor Electronics at Fraunhofer EAS. That choice can be driven by the commercial aspects, as well as the ratio of analog to digital components and the power budget for various use cases. It also can be affected by everything from sub-threshold design to transferring established techniques from digital to analog components, such as voltage scaling, clock-gating, duty-cycling and wake-up techniques. In addition, it can be impacted by time-to-digital approach for conversion, switched circuitry approaches, ultra-low-power local and global power management, sophisticated DC-to-DC converters as enablers, and ultra-low-power-optimized AMS design flows from model to layout.

And that’s just for starters. Power is the gating factor in most complex designs today, even if power management isn’t the primary goal of chipmakers.

“Chips are becoming more and more complex to accommodate maximum energy savings,” noted Godwin Maben, a Synopsys scientist. “Some estimates show the average number of power domains is greater than 20, but there are chips out there which have more than 200 or 300 power domains. There are a lot of different ways to reduce power, in addition to what you do at the architecture level. This can be done by tools automatically, provided it is given some vector input. If you have to reduce dynamic power specifically, you need to provide vectors that are truly representative and which can be used for optimization.”

Power optimization is not power optimized at RTL. It comes down to ensuring the final silicon or the tape-out data sees the same amount of optimization, he said. “If I optimize and get 10% reduction, I want to make sure that when I finalize or sign off the data the reduction is not 1%. This has to be handled throughout the flow, from synthesis to place-and-route to the ECO process.”

Dealing with all of these issues effectively requires a variety of different disciplines that historically never worked together. Power requires engineering teams to cross traditional silos, particularly as more parts of the design flow shift further to the left. This is evident at Mentor, a Siemens Business, where the advanced packaging tools group has been teaming with the physical verification group to develop open flows that allow for the assembly of complex, high-density advanced packaging systems.

Advanced packaging enables chipmakers to save power by reducing the distance that signals need to travel between memories, accelerators and various I/O blocks. It also enables them to use higher-bandwidth channels at slower transmission speeds, which can significantly reduce the amount of power required to move data back and forth between processors and memories.

“You can now drop an HBM (high-bandwidth memory module) on top of the package, and then do the routing and optimize the routing directly to that,” said Chris Cone, senior technical marketing engineer at Mentor. “When you compare that to the old days with a system-on-a-chip, where the interconnect is distributed laterally, now that you have the ability to stack it has a huge benefit on saving power and area.”

Advanced packaging techniques also make it possible to reduce power by designing functionality in the technology node that makes the most sense. “If you need to have a larger voltage interface, physical interface, you implement that at a more established node, then you do the processing, power, etc., in deep submicron technology,” Cone said. “These are the nodes that everybody knows about. Use whatever you can on a node where you already have a lot of data and learning and expertise.”

Another option that fits together with advanced packaging is silicon photonics, which is beginning to attract attention for chip-to-chip communication.

“With photonics, it’s all about joules per bit,” he said. “The way you work with photonics is you have to have the driver. You can try to make the electronic transistors on the same die as the photonics, which is hard to do, and then you usually make compromises in the both the photonics devices and the electronic devices. The better solution is to have drivers on separate die on the electronic die with an interface directly down into the photonics. This is another way to enable lower power technologies with this solution, 3D stacking or 3D multi-chip approaches.”

Silicon photonics has been making inroads in the data center for some time due to its ability to move data back and forth between processors and storage over long distances using very low power. But it also requires a different set of tradeoffs than traditional CMOS devices.

“Silicon photonics are big, so part of the tradeoff is that you rule out area from the equation,” said. Gilles Lamant, distinguished engineer at Cadence. “They are made out of glass, but for modulating light, for example, most of the devices that are in production are up to a micron long. The tradeoffs are different, and you can look at the qubit from IBM to actually get an idea of the tradeoffs. At the top of [the IBM quantum computer] there are huge weaved copper cables. This is because they need to go very fast with a very high bandwidth. If you look at that copper cable, you cannot put that in the pizza box in a data center, and it has nothing to do with temperature. It’s just huge and very expensive.”

Fig. 1: IBM’s qubit. Photo by Ann Steffora Mutschler/Semiconductor Engineering

This gets more complicated because copper is running out of steam.

“Typically, you’ve got copper from the AC, the switch, and everything going up to the front,” Lamant said. “Here you have that little plug-in photonic device that connects to the fiber running out of space in the front to put as many as you would want, and also the fact that it’s completely covered prevents ventilation so there isn’t air flow. What they’re really trying to do [in the datacenter] is replace the copper tracks, including between the DSP, the switch and everything, and get the photonic connection inside the box very close so they can get rid of that copper. So it’s big, but it is actually smaller than the physical plugins you would put in front—1mm or 2mm for each die. Consumption-wise, the laser consumes a lot of energy, but you can actually put it off-chip even though there are some advantages to having it on-chip. Globally, it’s actually more efficient to transmit light than to transmit electronics, and you also can go fairly long. From that perspective, it’s more efficient to use light versus electronics.”

So while it may appear large for a chip, in the context of a system it actually may take up less area than other types of connections. And that opens the door to significant improvements in bandwidth and throughput.

“When you have a processor, you have all those AI applications, they need to be fed data,” he said. “There is a very high bandwidth connection between processing and the other things. If you start separating them, or even if you try to put them together, you don’t have enough room to put all the copper tracks there to make the connection. Functionally, [silicon photonics] doesn’t have a match in copper, but copper still has a lot of good applications, and we need to find the sweet spots for photonics. It’s not going to replace everything everywhere. In this way it’s a bit like advanced RF I/Os. It’s required in certain places. It’s going to help tremendously in places. But if you think it’s going to be everywhere, or high-volume, you’re making a mistake.”

These types of challenges extend well beyond the data center. The electrification of vehicles requires energy efficiency because of the number of components that rely on a battery.

“All of the devices have to be power-efficient, said Annapoorna Krishnaswamy, product marketing manager in the Semiconductor Business Unit at ANSYS. “Otherwise, the battery is going to be supplying so much power to these electronic devices on the car that it will drain the battery too soon. But when it comes to applying power-saving techniques, it is becoming challenging to power gate these systems because you cannot put your devices to sleep and expect them to wake up in a reasonable amount of time. That adds latency and impacts performance. You have to be able to react, which means you cannot make a device sleep and expect to wake up and then react to a situation. As such, power gating is not a common technique, especially in automotive vision processors. Here, more clock-gating techniques are being employed.”

This also impacts AI designs, including the AI systems in cars. “AI is in its infancy right now, and the algorithms are continuously evolving,” Krishnaswamy said. “This means you must make sure that for the algorithms you are building, your hardware is power-efficient. You have to do power analysis much earlier, where you have the most opportunity for power saving. You need the ability to do it quickly enough so you have that idea up front rather than much later in the design cycle. Early power analysis is critical for AI-type of applications, because AI algorithms are changing.”

Security adds yet another challenge for power-sensitive designs, because the thin gate oxides and gate structures make them potential targets for side-channel attacks.

“In low power designs, side-channel security issues can be identified by looking at the voltage drop signature,” Krishnaswamy said. “You can encrypt the data that is being written into the system, or read out of it. That’s where it’s important to insulate your systems in such a way that you are not exposing that signature of your voltage drop pattern that can be read by a hacker. Chip power modeling techniques could analyze what the power integrity signature will look like so that the system is not prone to hackers.”

It’s not so easy to combine low-power and security in the same design. Depending upon the application, system architects have settled on securing certain parts of a design to balance those demands.

“In the data center, you cannot possibly try to secure the entire system, because it’s so high performance and it consumes so much power,” said Helena Handschuh, security technologies fellow at Rambus. “You want to design a very tiny subsystem that will provide the security to boot up in a space that is considered yours at that point. Once the security portion of that is done and performed, then you can unleash the power of the rest of the system and have the high performance computing going on. The solution I’m advocating is to have a tiny subsystem as a separate little piece that will provide security functionality. Because it’s so much smaller and simpler, it will consume much less than the rest of the entire system, and that the rest of the system work at its regular hardware.”

In simple terms, security isn’t free. “There will be an impact on the power consumption,” said Mike Eftimakis, director of business innovation strategy at Arm. “There will possibly be an impact on the performance of the system, depending on what you consider as the operation in the context of what you are doing. And there will be an impact on the area, as well. All of this depends on what is designed and the type of system that you have. If you have a system where everything is more self-contained, the impact of security will be on the isolation within the different elements. That will be mostly software, software processing, which will impact the total performance of the system. In some other cases, you will have to consider the attacks that can come through the different ports of the device, and this will require some actual hardware to manage. It can be more or less complicated, depending on the level of security that you expect.”

Arm introduced its Platform Security Architecture last year, which establishes an overall framework for integrating different layers of security. “Basically, the more security you want, the more impact it will have on the system. When you add security, you will need to consider the threats that apply to the device. It will always be case by case.”

There are multiple design-specific costs that need to be considered, as well. For example, systems need to be added to manage the security. There also are variable costs depending upon how fast security needs to react to potential breaches.

“If you have authentication of the system, how fast do you want this authentication to happen,” said Eftimakis. “You can do slow authentication with a small system. But if you want to have fast authentication, you will have to have accelerators in your hardware. You would have to have larger devices. It will take time and it will take power. But maybe there’s a tradeoff because if you use power for a short period of time, so you might get a performance boost at a certain point. As a rule of thumb, the more security you want, the more expensive it will be for your system. That means you have to be very careful when you do the analysis. Consider the threats that apply to your device and not to the blanket ‘security for everything.’”

Too much security can have an adverse impact. “In some cases, it can give you a false sense of security, because you may have forgotten to secure another part of the system,” he noted. “They say, ‘I encrypt my keys, I store them in a secure element, etc.’ Perfect, this part is good. But did you think about all the threats that could apply to the device and maybe just the link to the server is weak? In that case, it can be hacked, and people can then compromise the device. So it’s important to really think about the whole system and put in the security that is really needed.”

There is a growing list of challenges for low-power, power-sensitive, and energy-efficient SoC designs today. There are more application areas, more variables in every design, and more uncertainty about how some of of these designs will need to evolve as new markets take shape. And there are more disciplines being drawn into solving this growing list of issues, from design to verification to security.

Power has always been a complex issue, but it is one that many more engineers are running up against, regardless of their focus area. And for everyone involved, it is becoming even more complex than it was in the past. It’s now everyone’s problem, and that problem is spreading out.

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