Toward Consistent Circuit-Level Aging Simulations In Different EDA Environments

The impact of using degradation models in different environments.


Aging simulations on circuit level allow integrated circuit (IC) designers to verify their circuits with respect to lifetime reliability requirements by considering the degradation of field effect transistors (FETs). To obtain significant analysis results with a reasonable effort, two prerequisites have to be fulfilled. First, reasonable models for FET degradation effects have to be set up. Second, the models have to be implemented into electronic design automation (EDA) environments. In this work, we demonstrate that degradation models can be implemented consistently in different EDA environments by using tool-specific and generic modeling interfaces. Furthermore, we compare the behavior of selected environments based on simulation studies with example degradation models for bias temperature instability (BTI) and hot carrier injection (HCI).

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