tag: Fraunhofer IIS EAS

Enhancing The Energy-Efficient Production of Tempered Glass By Using Simulation-Based Optimization
By Fraunhofer IIS/EAS - 11 Apr, 2018 - Comments: 0

In many industrial manufacturing processes energy use is one of the most important cost factors. Especially in energy-intensive industries like steel production or glass processing minimizing energy use is a key measure to save resources and reduce manufacturing costs. The research project OptPlanEnergie concentrates on the production of tempered glass. In this project we apply simulation and o... » read more

Choosing The Right Interconnect
By Ed Sperling - 09 Apr, 2018 - Comments: 3

Efforts to zero in on cheaper advanced packaging approaches that can speed time to market are being sidetracked by a dizzying number of choices. At the center of this frenzy of activity is the [getkc id="36" kc_name="interconnect"]. Current options range from organic, silicon and glass interposers, to bridges that span different die at multiple levels. There also are various fan-out approach... » read more

The Analog Design Gap
By Benjamin Prautsch - 08 Mar, 2018 - Comments: 0

By Benjamin Prautsch and Torsten Reich Sensors are everywhere. In the context of Industry 4.0 and IoT, we face an ever-increasing demand for high-quality sensing. Data acquisition is fundamental to adaptive production chains. So aggregating data isn't just some nice-to-have feature. It is the basis of modern production systems. But don’t we have sensors already? Isn’t everything fine?... » read more

Why All Nodes Won’t Work
By Ed Sperling - 08 Mar, 2018 - Comments: 4

A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

Application Of Richardson Extrapolation To The Co-Simulation Of FMUs From Building Simulation
By Fraunhofer IIS/EAS - 07 Mar, 2018 - Comments: 0

The application of the FMI technology gains ground in building simulation. As far as specialized tools support the FMI simulator coupling becomes an important option to simulate complex building models. Co-simulation needs a master algorithm which controls the communication time steps as well as the signal exchange between FMUs. Often a constant communication step size is applied chosen by the ... » read more

Toward High-End Fan-Outs
By Ed Sperling - 05 Mar, 2018 - Comments: 1

Foundries and OSATs are working on more advanced fan-outs, including some with vertically stacked die inside the package, filling a middle ground between lower-cost fan-outs and systems in package on one side and 2.5D and 3D-ICs on the other. These new [getkc id="202" kc_name="fan-outs"] have denser interconnects than previous iterations, and in some cases they include multiple routing layer... » read more

Chip Aging Accelerates
By Ed Sperling - 14 Feb, 2018 - Comments: 1

Reliability is becoming an increasingly important proof point for new chips as they are rolled out in new markets such as automotive, cloud computing and industrial IoT, but actually proving that a chip will function as expected over time is becoming much more difficult. In the past, reliability generally was considered a foundry issue. Chips developed for computers and phones were designed ... » read more

Avoiding Down Times: Monitoring, Diagnostics And Troubleshooting Of Industrial Wireless Systems
By Fraunhofer IIS/EAS - 07 Feb, 2018 - Comments: 0

The ever-growing proliferation of wireless devices and technologies used for Internet of Things (IoT) applications, such as patient monitoring, military surveillance, and industrial automation and control, has created an increasing need for methods and tools for connectivity prediction, information flow monitoring, and failure analysis to increase the dependability of the wireless network. Inde... » read more

Turning Down The Power
By Jeff Dorsch - 11 Jan, 2018 - Comments: 0

Chip and system designers are giving greater weight to power issues these days. But will they inevitably hit a wall in accounting for ultra-low-power considerations? Performance, power, and area are the traditional attributes in chip design. Area was originally the main priority, with feature sizes constantly shrinking according to Moore's Law. Performance was in the saddle for many years. M... » read more

Mixed-Signal Issues Worse At 10/7nm
By Ann Mutschler - 03 Jan, 2018 - Comments: 1

Despite increasingly difficulty in scaling digital logic to 10/7nm, not all designs at the leading edge are digital. In fact, there are mixed-signal components in designs at almost all nodes down to 10/7nm. This may seem surprising because analog scaling has been an issue since about 90nm, but these are not traditional analog components. Analog IP increasingly includes highly integrated, mix... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy