tag: Fraunhofer IIS EAS

Driving With Chiplets
By Andy Heinig - 24 Sep, 2019 - Comments: 0

The first examples of the upper class of vehicles that can drive autonomously on the highway already have arrived on the market or will be introduced to the market in the coming years. Travel on the highway was selected as the first application because the number of objects that have to be taken into account in front of, next to, and behind the vehicle is manageable. This means the required ... » read more

3D Power Delivery
By Brian Bailey - 12 Sep, 2019 - Comments: 1

Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels. The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emph... » read more

Trading Off Power And Performance Earlier In Designs
By Ann Mutschler - 12 Sep, 2019 - Comments: 0

Optimizing performance, power and reliability in consumer electronics is an engineering feat that involves a series of tradeoffs based on gathering as much data about the use cases in which a design will operate. Approaches vary widely by market, by domain expertise, and by the established methodologies and perspective of the design teams. As a result, one team may opt for a leading-edge des... » read more

Taking Energy Into Account
By Ann Mutschler - 28 Aug, 2019 - Comments: 1

Considering power throughout the SoC design flow is common practice. The same cannot be said for energy, although that is beginning to change as chips increasingly incorporate heterogeneous processing elements. Combined with this, AI/ML/DL technologies increasingly allow engineering teams to explore and optimize design data for more targeted and efficient systems. But this approach also requ... » read more

Getting To Tape-Out Quicker With Analog Layout Generators
By Benjamin Prautsch - 08 Aug, 2019 - Comments: 0

All design engineers know it well: there is hardly any time left until tape-out, but the amount of work that remains is not decreasing as fast as the deadline is approaching. The intricate schematic must still be implemented as a layout, and many recurring tasks slow down the progress. The real crux often lies in specific parts of the circuit – parts that often have lower performance demands ... » read more

Determining Where Power Analysis Matters Most
By Ann Mutschler - 08 Aug, 2019 - Comments: 0

How much accuracy is required in every stage of power analysis is becoming a subject of debate, as engineering teams wrestle with a mix of new architectures, different use cases and increasing pressure to get designs out on time. The question isn't whether power is a critical factor in designs anymore. That is a given. It is now about the most efficient way to tackle those issues, as well as... » read more

Benchmarking Workshop On (Active) Vibration Damping
By Fraunhofer IIS/EAS - 07 Aug, 2019 - Comments: 0

Benchmarking workshops (also called mechathons when held in the area of mechatronics) can be used to benchmark existing technologies and bring together experts of the same field in order to encourage knowledge transfer and future cooperation. Within the frameworks of the Comet K2 Research Center “Symbiotic Mechatronics“ of the Linz Center of Mechatronics (LCM) and the “Mechatronics Allian... » read more

Hardware-Software Co-Design Reappears
By Brian Bailey - 25 Jul, 2019 - Comments: 1

The core concepts in hardware-software co-design are getting another look, nearly two decades after this approach was first introduced and failed to catch on. What's different this time around is the growing complexity and an emphasis on architectural improvements, as well as device scaling, particularly for AI/ML applications. Software is a critical component, and the more tightly integrate... » read more

Low-Power Design Becomes Even More Complex
By Ann Mutschler - 16 Jul, 2019 - Comments: 0

Throughout the SoC design flow, there has been a tremendous amount of research done to ease the pain of managing a long list of power-related issues. And while headway has been made, the addition of new application areas such as AI/ML/DL, automotive and IoT has raised as many new problems as have been solved. The challenges are particularly acute at leading-edge nodes where devices are power... » read more

From Constraints to Tape-Out: Towards A Continuous AMS Design Flow
By Fraunhofer IIS/EAS - 15 Jul, 2019 - Comments: 0

The effort in designing analog/mixed-signal (AMS) integrated circuits is characterized by the largely manual work involved in the design of analog cells and their integration into the overall circuit. This inequality in effort between analog and digital cells increases with the use of modern, more complex technology nodes. To mitigate this problem, this paper presents four methods to improve ex... » read more

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