Preparing For Ferroelectric Devices

By Katherine Derbyshire - 02 Oct, 2024 - Comments: 0

The discovery of ferroelectricity in materials that are compatible with integrated circuit manufacturing has sparked a wave of interest in ferroelectric devices. Ferroelectrics are materials with a permanent polarization, the direction of which can be switched by an applied field. This polarization can be used to raise or lower the threshold voltage of a transistor, as in FeFETs, or it can c... » read more

Chip Industry Week In Review

By The SE Staff - 27 Sep, 2024 - Comments: 0

Global spending on 300mm fab equipment is expected to reach a record US$400 billion from 2025 to 2027, according to SEMI. Key drivers are the regionalization of semiconductor fabs and the increasing demand for AI chips in data centers and edge devices, with China, South Korea, and Taiwan leading the way. The Biden-Harris Administration launched the National Semiconductor Technology Center’... » read more

Technical Paper Round-Up: July 5

By Linda Christensen - 05 Jul, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=36 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

One Transistor Process-in-Memory Device Strategy w/ Multi-Functional Multi-Gate One-transistor (MGT) Design of Multiple Electrodes

By Technical Paper Link - 04 Jul, 2022 - Comments: 0

New technical paper titled "Multi-functional multi-gate one-transistor process-in-memory electronics with foundry processing and footprint reduction" from researchers at Ningbo Institute of Materials Technology and Engineering (Chinese Academy of Sciences), Center of Materials Science and Optoelectronics Engineering (University of Chinese Academy of Sciences), Shanghai Institute of Microsystem ... » read more

Making PUFs Even More Secure

By Bryon Moyer - 06 Jan, 2022 - Comments: 0

As security has become a must-have in most systems, hardware roots of trust (HRoTs) have started appearing in many chips. Critical to an HRoT is the ability to authenticate and to create keys – ideally from a reliable source that is unviewable and immutable. “We see hardware roots of trust deployed in two use models — providing a foundation to securely start a system, and enabling a se... » read more

Thinner Channels With 2D Semiconductors

By Katherine Derbyshire - 21 Jun, 2021 - Comments: 0

Moving to future nodes will require more than just smaller features. At 3/2nm and beyond, new materials are likely to be added, but which ones and exactly when will depend upon an explosion of material science research underway at universities and companies around the globe. With field-effect transistors, a voltage applied to the gate creates an electric field in the channel, bending the ban... » read more

A Novel PUF Using Stochastic Short-Term Memory Time of Oxide-Based RRAM for Embedded Applications

By Technical Paper Link - 31 Mar, 2021 - Comments: 0

Abstract: "RRAM suffers from poor retention with short-term memory time when using low compliance current for programing. However, the short-term memory time exhibits ideal randomness, which can be exploited as an entropy source for physically unclonable function (PUF). In this work, we demonstrated a novel PUF utilizing the stochastic short-term memory time of oxide-based RRAM. The proposed P... » read more

A Machine-Learning-Resistant 3D PUF with 8-layer Stacking Vertical RRAM and 0.014% Bit Error Rate Using In-Cell Stabilization Scheme for IoT Security Applications

By Technical Paper Link - 03 Mar, 2021 - Comments: 0

Abstract: "In this work, we propose and demonstrate a multi-layer 3-dimensional (3D) vertical RRAM (VRRAM) PUF with in-cell stabilization scheme to improve both cost efficiency and reliability. An 8-layer VRRAM array was manufactured with excellent uniformity and good endurance of >10 7 . Apart from the variation in RRAM resistance, enhanced randomness is obtained thanks to the parasitic IR... » read more

Power/Performance Bits: Feb. 8

By Jesse Allen - 08 Feb, 2021 - Comments: 0

Transparent sensor Researchers at Osaka University created a thin, flexible, transparent sensor using silver nanowire networks. High-resolution printing was used to fabricate the centimeter-scale cross-aligned silver nanowire arrays, with reproducible feature sizes from 20 to 250 micrometers. As a proof-of-concept for functionality, they used their arrays to detect electrophysiological signals... » read more

Power/Performance Bits: Dec. 3

By Jesse Allen - 03 Dec, 2019 - Comments: 0

Waking up IoT devices Researchers at UC San Diego developed an ultra-low power wake-up receiver chip that aims to reduce the power consumption of sensors, wearables, and Internet of Things devices that only need to communicate information periodically. "The problem now is that these devices do not know exactly when to synchronize with the network, so they periodically wake up to do this eve... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?