Week In Review: Manufacturing, Test


Chipmakers and OEMs At next week’s Apple Worldwide Developers Conference, Apple is expected to roll out its long-awaited Arm-based Mac computers. This could provide a boost for Apple’s foundry vendor as well as equipment makers. It’s the worst-kept secret in the industry. As reported by the Apple sites, Apple is moving from Intel’s microprocessors to its own Arm-based chips for th... » read more

The Next Advanced Packages


Packaging houses are readying their next-generation advanced IC packages, paving the way toward new and innovative system-level chip designs. These packages include new versions of 2.5D/3D technologies, chiplets, fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers and panels. One is... » read more

Week In Review: Manufacturing, Test


Chipmakers Jim Keller, senior vice president in the Technology, Systems Architecture and Client Group (TSCG) and general manager of the Silicon Engineering Group (SEG) at Intel, has resigned amid a major reorganization at the company. Here's one report about the situation. Cree as well as China’s Yutong Group and StarPower are working together to accelerate the commercial adoption of sili... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs Senator Patrick Leahy (D-Vt.), Senator Chuck Schumer (D-N.Y.) and Senator Jack Reed (D-R.I.) have sent a letter to officials from the Trump administration, demanding answers about TSMC’s recent announcement to build a fab in Ariz. As reported, TSMC has announced its intention to build and operate an advanced semiconductor fab in the U.S. The fab, to be built in Arizona, w... » read more

‘More Than Moore’ Reality Check


The semiconductor industry is embracing multi-die packages as feature scaling hits the limits of physics, but how to get there with the least amount of pain and at the lowest cost is a work in progress. Gaps remain in tooling and methodologies, interconnect standards are still being developed, and there are so many implementations of packaging that the number of choices is often overwhelming. ... » read more

Blog Review: May 13


Mentor's Neil Johnson considers when in a project certain verification methods should be deployed and the relative impact of techniques at a given point in subsystem design. Cadence's Paul McLellan looks back at the development of mobile standards with 2G, GSM, and the transition to all-digital transmission. Synopsys' Taylor Armerding highlights five online courses to boost your software ... » read more

Big Changes For eFPGAs


Geoff Tate, CEO of Flex Logix, talks with Semiconductor Engineering about the state of embedded FPGAs, why this is easier for some companies than others, why this is important for adding flexibility into an ASIC, and what are the main applications for this technology. » read more

Week In Review: Design, Low Power


Si2 launched an industry-wide survey to identify planned usage and structural gaps for prioritizing and implementing artificial intelligence and machine learning in EDA. A recently formed Si2 Special Interest Group is conducting the survey as part of an effort to identify where industry collaboration will help eliminate deficiencies caused by a lack of common languages, data models, labels, and... » read more

NVM Reliability Challenges And Tradeoffs


This second of two parts looks at different memories and possible solutions. Part one can be found here. While various NVM technologies, such as PCRAM, MRAM, ReRAM and NRAM share similar high-level traits, their physical renderings are quite different. That provides each with its own set of challenges and solutions. PCRAM has had a fraught history. Initially released by Samsung, Micron, a... » read more

Designing Ultra Low Power AI Processors


AI chip design is beginning to shift direction as more computing moves to the edge, adding a level of sophistication and functionality that typically was relegated to the cloud, but in a power envelope compatible with a battery. These changes leverage many existing tools, techniques and best practices for chip design. But they also are beginning to incorporate a variety of new approaches tha... » read more

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