How Many Nanometers?


What’s the difference between a 10nm and a 7nm chip? That should be a straightforward question. Math, after all, is the only pure science. But as it turns out, the answer is hardly science—even if it is all about numbers. Put in perspective, at 65nm, companies defined the process node by the half pitch of the first metal layer. At 40/45nm, with the cost and difficulty of developing n... » read more

To 10nm And Beyond


Hong Hao, senior vice president of the foundry business at Samsung Semiconductor, sat down with Semiconductor Engineering to discuss the future direction of transistors, process technology, lithography and other topics. What follows are excerpts of those conversations. SE: Samsung recently rolled out its 10nm finFET technology. It appears that Samsung is the world’s first company to ship 1... » read more

Will There Be Enough Silicon Wafers?


The silicon wafer industry, a critical part of the IC supply chain, is undergoing a new and perhaps alarming wave of merger and acquisition activity. While consolidation in this sector is not new, the pace of M&A activity is picking up and there are fewer companies left. Silicon wafer makers produce and sell raw silicon wafers to chipmakers, which process them into chips. But despite con... » read more

What Happened To Inverse Lithography?


Nearly 10 years ago, the industry rolled out a potentially disruptive technique called inverse lithography technology (ILT). But ILT was ahead of its time, causing the industry to push out the technology and relegate it to niche-oriented applications. Today, though, ILT is getting new attention as the semiconductor industry pushes toward 7nm, and perhaps beyond. ILT is not a next-generation ... » read more

10nm FinFET Market Heats Up


The 10nm finFET market is heating up in the foundry business amid the ongoing push to develop chips at advanced nodes. Not long ago, Intel announced its 10nm finFET process, with plans to ramp up the technology in 2017. Then, TSMC recently introduced its 10nm process, with plans to move into production by the fourth quarter of 2016. Now, Samsung Electronics said that it has commenced mass... » read more

The Week In Review: Manufacturing


Chipmakers Alain Kaloyeros, president of SUNY Polytechnic Institute, has resigned. This comes amid charges that Kaloyeros was involved in an alleged bid-rigging scheme, according to multiple reports. SUNY Poly, a high-tech educational ecosystem in New York, was recently formed from the merger of the SUNY College of Nanoscale Science and Engineering (CNSE) and the SUNY Institute of Technology. ... » read more

Blog Review: Oct. 5


Mentor's Michael White explores why established nodes are experiencing such an unexpectedly long lifespan and how that is driving new challenges for designers. Cadence's Ann Keffer checks out the history of Ethernet and how it won the battle to become the dominant network protocol. Is your IoT device fueling a botnet? Vulnerable firmware on internet connected devices was behind one of the... » read more

The Week In Review: Manufacturing


Chipmakers In 2016, growth in the pure-play foundry business will be driven by leading-edge processes, according to IC Insights. In fact, the increase in pure-play foundry sales this year is forecast to be almost entirely due to processes at » read more

Packaging Wars Begin


The advanced IC-packaging market is turning into a high-stakes competitive battleground, as vendors ramp up the next wave of [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D"] technologies, high-density fan-out packages and others. At one time, the outsourced semiconductor assembly and test ([getkc id="83" comment="OSAT"]) vendors dominated and handled the chip-packaging requirement... » read more

450mm And Other Emergency Measures


Talk about boosting wafer sizes from 300mm to 450mm has been creeping back into presentations and discussions at conferences over the past couple months. Earlier this year, discussions focused on panel-level packaging. These are basically similar approaches to the same problem, which is that wafers need to be larger to reap efficiencies out of device scaling. Whether either of these approach... » read more

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