To 10nm And Beyond

Samsung foundry exec discusses the company’s strategy.


Hong Hao, senior vice president of the foundry business at Samsung Semiconductor, sat down with Semiconductor Engineering to discuss the future direction of transistors, process technology, lithography and other topics. What follows are excerpts of those conversations.

SE: Samsung recently rolled out its 10nm finFET technology. It appears that Samsung is the world’s first company to ship 10nm finFETs in production, beating its rivals to the punch. Is that the case?

Hao: For 10nm, we are announcing that we have started production. We will be the first one to production at the 10nm node.

SE: Samsung’s first-generation 10nm process is called 10LPE. What does 10nm finFET technology bring to the party, as compared to 14nm finFETs?

Hao: 10nm brings a lot of benefits to our customers in terms of area scaling, performance and power or PPA. So overall, the PPA improvements are very substantial compared 14nm. We have compared that in terms of the performance, area and power to 14nm LPE. 14nm LPE is our first-generation finFET technology. We see up to a 30% area reduction with a 27% performance improvement or 40% lower power at the same performance.

SE: What’s the different between your 14nm and 10nm finFET technologies in terms of fin structures and other aspects?

Hao: We are improving the fin structures going from 14nm to 10nm.

SE: Samsung is using 193nm immersion and double patterning at 14nm. At 10nm, Samsung is using 193nm immersion. What’s different between 14nm and 10nm?

Hao: We introduced triple patterning in select ways to make the design more efficient.

SE: Can you discuss the interconnect pitch? Is it a true 10nm backend?

Hao: I won’t be able to give you more specifics beyond what we have provided.

SE: What are the apps for the leading edge?

Hao: Typically, in the past, we have gone into production first with mobile products. That followed with other products in consumer. Recently, we’ve focused heavily on networking, automotive and computing.

SE: When will Samsung’s 10nm process ship? What about the products?

Hao: For system-on-chip products for mobile digital devices, those will be announced in early 2017. Our shipments will actually begin within this year. So, our 10LPE process is going into production. Following that, we have previously announced our second-generation technology, 10LPP. 10LPP will be enhanced with an additional performance boost. The production timeline for 10LPP remains on track for the second half of 2017.

SE: Some of your competitors believe 10nm will be a short node or are skipping it altogether. Any thoughts?

Hao: We believe 10nm will be a long node. 10nm will offer substantial improvements over 14nm.

SE: What’s next?

Hao: The next node is 7nm. There is a lot of confusion in the industry as to what 7nm means. Our 7nm is going to be full-node scaling from 10nm. It’s going to be EUV-based. Our 7nm based on EUV will be another major leap in overall PPA. The 7nm node will be a major node for us. So, we will have 14nm, 10nm and 7nm processes. All three nodes, we believe, will be long and major nodes.

SE: When will Samsung introduce 7nm?

Hao: We think we will maintain our typical cadence. But I won’t be able to be more specific than that.

SE: What is your cadence?

Hao: This roughly two-year cadence works well with our customer base.

SE: TSMC plans to extend 193nm and multiple patterning to 7nm. Yet, Samsung plans to insert extreme ultraviolet (EUV) lithography at 7nm. What’s behind this strategy?

Hao: At this point, we are really pushing against the wall is terms of not having EUV and relying on only immersion litho. 7nm, without EUV, will push the technology too hard. It will result in a much higher mask layer count and a much higher complexity in fabrication. It will result in a much higher cost in the design and much longer turnaround times throughout the design and fabrication phase. This will lead to a longer product development cycle.

SE: What’s the bottom line?

Hao: 7nm, without EUV, will be a costly node in terms of not only fabrication, wafer costs and mask costs, but also design costs and development times. 7nm, without EUV, will be a short node.

SE: Anything else?

Hao: We’ve explained to customers our logic as to why 7nm without EUV will be short-lived. When EUV comes along, there is no reason to have such a high layer count and complexity. We believe that EUV-based technology will take over very quickly.

SE: Still, the big question is clear–Will EUV ever happen? After years of development, EUV is still not in production amid issues with the source, resists and mask infrastructure. Right now, EUV is targeted for 7nm. It could slip to 5nm or fail altogether. Any comments here?

Hao: We believe we are making very good progress here. This is not only our system LSI group, but also our DRAM division. Together, along with the overall semiconductor business, we have been very active in pushing EUV technology and production readiness.

SE: Going forward, foundry customers will have many choices, such as 14nm, 10nm and 7nm finFETs. Then, of course, Samsung has planar 28nm technology, based on both bulk and fully-depleted silicon-on-insulator (FD-SOI). How will all this play out?

Hao: We see customers making decisions based on their technology needs and products. At 28nm, we still have active engagements. We see a lot of people still starting new designs at 14nm. But for customers who demand high performance and a higher level of integration, they are certainly moving to 10nm. This certainly applies to the mobile application processors. The high-performance computing and networking customers are also very interested in this.

SE: Recently, GlobalFoundries announced a 12nm version of FD-SOI. Does that compete against 14nm and/or 10nm finFETs?

Hao: I won’t comment on that technology.

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