Week In Review: Manufacturing, Test


Government funding President Biden signed the CHIPS and Science Act into law on Tuesday, saying “America is back and leading the way.” That same day Micron touted a $40 billion investment through to 2030, which it expects will create 40,000 American jobs. “This legislation will enable Micron to grow domestic production of memory from less than 2% to up to 10% of the global market in t... » read more

Week In Review, Manufacturing, Test


Post-CHIPS Act Micron is discussing a potential new fab that could employ thousands of workers, following the passage of the Chips and Science Act. Idaho is hoping it will be built near its headquarters facilities in Boise, but Micron hasn’t committed publicly. Rob Beard, senior vice president, general counsel and corporate secretary at Micron, told the Idaho Statesman the company is consi... » read more

Bespoke Silicon Redefines Custom ASICs


Semiconductor Engineering sat down to discuss bespoke silicon and what's driving that customization with Kam Kittrell, vice president of product management in the Digital & Signoff group at Cadence; Rupert Baines, chief marketing officer at Codasip; Kevin McDermott, vice president of marketing at Imperas; Mo Faisal, CEO of Movellus; Ankur Gupta, vice president and general manager of Siemens... » read more

Fab Investments Head Toward Record High


Corporations and governments around the globe are making record-breaking investments in chip manufacturing plants amid a major push to make the semiconductor supply chain more robust and less prone to shortages caused by everything from market variations to geopolitical interruptions. These investments — which range from updating existing fabrication facilities to building entirely new fab... » read more

Hybrid Bonding Moves Into The Fast Lane


The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

Week in Review: Manufacturing, Test


Fab capacity STMicroelectronics and GlobalFoundries inked a deal to build a new jointly-operated 300mm fab adjacent to ST’s existing 300mm facility in Crolles, France. This facility is targeted to ramp at full capacity by 2026, with up to 620,000 300mm wafer per year production at full build-out (~42% ST and ~58% GF). The new facility will support several technologies, with a special focus... » read more

Finding Frameworks For End-To-End Analytics


End-to-end analytics can improve yield and ROI on tool purchases, but reaping those benefits will require common data formats, die traceability, an appropriate level of data granularity — and a determination of who owns what data. New standards, guidelines, and consortium efforts are being developed to remove these barriers to data sharing for analytics purposes. But the amount of work req... » read more

Week In Review, Manufacturing, Test


The U.S. is attempting to restrict sales of ASML’s deep ultra-violet (DUV) litho systems to China, according to a report from Bloomberg. The U.S. has been working to limit China's access to advanced technology for some time, and it has already limited sales of extreme ultra-violet (EUV), which is used to develop chips at the most advanced process nodes. DUV, in contrast, is used for older-nod... » read more

Week In Review: Manufacturing, Test


Notes from the fabs Intel warned the “scope and pace" of the Ohio fab buildout could be impacted due to U.S. Congress’ inaction on funding the $52 billion CHIPS Act. The facility was announced in January with an initial phase investment of more than $20 billion with a larger expansion up to $100 billion over the next decade. The initial phase is not expected to be impacted, other than a de... » read more

Variation Making Trouble In Advanced Packages


Variation is becoming increasingly problematic as chip designs become more heterogeneous and targeted by application, making it difficult to identify the root cause of problems or predict what can go wrong and when. Concerns about variation traditionally have been confined to the most advanced nodes, where transistor density is highest and where manufacturing processes are still being fine-t... » read more

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