Week In Review: Auto, Security, Pervasive Computing


The U.S. Cybersecurity and Infrastructure Security Agency (CISA) issued a cybersecurity warning about Chinese state-sponsored activity impacting networks across U.S. critical infrastructure. “One of the actor’s primary tactics, techniques, and procedures (TTPs) is living off the land, which uses built-in network administration tools to perform their objectives," the agency said. Hacking eff... » read more

Chip Industry’s Technical Paper Roundup: May 23


New technical papers recently added to Semiconductor Engineering’s library: [table id=104 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us... » read more

Solving Memory Mapping Issues with Deep RL (Google)


A technical paper titled "Optimizing Memory Mapping Using Deep Reinforcement Learning" was published by Google DeepMind and Google. Abstract: "Resource scheduling and allocation is a critical component of many high impact systems ranging from congestion control to cloud computing. Finding more optimal solutions to these problems often has significant impact on resource and time savings, red... » read more

Week In Review: Design, Low Power


Design Ansys has signed a definitive agreement to acquire EDA tool company Diakopto. Diakopto specializes in software tools that find the cause of layout parasitics. Its products are ParagonX, for analyzing and debugging IC designs and layout parasitics, and EM/IR analysis/verification tool PrimeX. The deal is expected to close in the second quarter of 2023. SEMI’s FlexTech community issu... » read more

Week In Review: Design, Low Power


Synopsys acquired Silicon Frontline Technology, a provider of an electrical layout verification solution for mixed-signal and analog designs, large-scale power semiconductor devices, and electrostatic discharge protection networks. "This acquisition enables Synopsys to extend the capabilities of our design analysis portfolio and help build out a system-level electrical analysis platform. We als... » read more

Pinpointing Timing Delays Can Improve Chip Reliability


Growing pressure to improve IC reliability in safety- and mission-critical applications is fueling demand for custom automated test pattern generation (ATPG) to detect small timing delays, and for chip telemetry circuits that can assess timing margin over a chip's lifetime. Knowing the timing margin in signal paths has become an essential component in that reliability. Timing relationships a... » read more

Week In Review: Auto, Security, Pervasive Computing


Pervasive computing Microsoft and AMD are working together on an AI processor, according to a report in Bloomberg. Tenstorrent adopted Arteris IP’s Ncore and FlexNoC interconnect IP for its AI RISC-V chiplets. The chiplets will be configurable for different uses and workloads. Some use cases include AI high-performance computing for data center, such as cloud servers, and edge devices and... » read more

New Standards Push Co-Packaged Optics


Co-packaged optics (CPOs) promise five times the bandwidth of pluggable connections, but the new architecture requires multiple changes to accommodate different applications. The Optical Internetworking Forum (OIF) recently published standards for co-packaged optics, which are the photonic industry’s hope for handling today’s faster Ethernet interfaces, as well as increasing speeds and p... » read more

Chip Industry’s Technical Paper Roundup: Apr. 25


New technical papers recently added to Semiconductor Engineering’s library: [table id=94 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Hyperscale HW Optimized Neural Architecture Search (Google)


A new technical paper titled "Hyperscale Hardware Optimized Neural Architecture Search" was published by researchers at Google, Apple, and Waymo. "This paper introduces the first Hyperscale Hardware Optimized Neural Architecture Search (H2O-NAS) to automatically design accurate and performant machine learning models tailored to the underlying hardware architecture. H2O-NAS consists of three ... » read more

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