Microarchitectural Side-Channel Attacks And Defenses On Non-Volatile RAM


A new technical paper titled "NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems" was written (preprint) by researchers at UC San Diego, UT Austin, and Purdue University. Abstract "We study microarchitectural side-channel attacks and defenses on non-volatile RAM (NVRAM) DIMMs. In this study, we first perform reverse-engineering of NVRAMs as implemented by the Intel Optane... » read more

Review of Methods to Design Secure Memristor Computing Systems


A technical paper titled "Review of security techniques for memristor computing systems" was published by researchers at Israel Institute of Technology, Friedrich Schiller University Jena (Germany), and Leibniz Institute of Photonic Technology (IPHT). Abstract "Neural network (NN) algorithms have become the dominant tool in visual object recognition, natural language processing, and robotic... » read more

Formal Processor Model Providing Secure Speculation For The Constant-Time Policy


A technical paper titled "ProSpeCT: Provably Secure Speculation for the Constant-Time Policy (Extended version)" was published by researchers at imec-DistriNet at KU Leuven, CEA, List, Université Paris Saclay and INRIA. Abstract: "We propose ProSpeCT, a generic formal processor model providing provably secure speculation for the constant-time policy. For constant-time programs under a no... » read more

HW-SW Co-Design Solution For Building Side-Channel-Protected ML Hardware


A technical paper titled "Hardware-Software Co-design for Side-Channel Protected Neural Network Inference" was published (preprint) by researchers at North Carolina State University and Intel. Abstract "Physical side-channel attacks are a major threat to stealing confidential data from devices. There has been a recent surge in such attacks on edge machine learning (ML) hardware to extract the... » read more

Detecting Hardware Trojans In a RISC-V Core’s Post-Layout Phase


A new technical paper "Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study" was published by researchers at University of Bremen, DFKI GmbH, and the German Aerospace Center. Abstract: "With the exponential increase in the popularity of the RISC-V ecosystem, the security of this platform must be re-evaluated especially for mission-critical and IoT d... » read more

RSFQ Logic Based Logic Locking Technique For Immunizing Against SAT-Based Attacks


A new technical paper titled "C-SAR: SAT Attack Resistant Logic Locking for RSFQ Circuits" was published (preprint) by researchers at University of Southern California. Abstract: "Since the development of semiconductor technologies, exascale computing and its associated applications have required increasing degrees of efficiency. Semiconductor-transistor-based circuits (STbCs) have strugg... » read more

Side-Channel Attacks Via Cache On the RISC-V Processor Configuration


A technical paper titled "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment" was published by researchers at University of Electro-Communication, Academy of Cryptography Techniques, Technology Research Association of Secure IoT Edge Application based on RISC-V Open Architecture (TRASIO), and AIST. "This work proposed a cross-process exploitation ... » read more

Hardware Trojan Detection Case Study Based on 4 Different ICs Manufactured in Progressively Smaller CMOS Process Technologies


A technical paper titled "Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations" was published by researchers at Max Planck Institute for Security and Privacy, Université catholique de Louvain (Belgium), Ruhr University Bochum, and Bundeskriminalamt. "In this work, we aim to improve upon this state of the art by presenting a... » read more

How Secure Are RISC-V Chips?


When the Meltdown and Spectre vulnerabilities were first uncovered in 2018, they heralded an industry-wide shift in perspective regarding processor security. As the IBM X-Force Threat Intelligence Index put it the following year, "2018 ushered in a new era of hardware security challenges that forced enterprises and the security community to rethink the way they approach hardware security." R... » read more

Hardware Fuzzing (U. of Michigan, Google, Virginia Tech)


A technical paper titled "Fuzzing Hardware Like Software" was published by researchers at University of Michigan, Google and Virginia Tech. The paper was presented at the 2022 Usenix Security Symposium. Abstract: "Hardware flaws are permanent and potent: hardware cannot be patched once fabricated, and any flaws may undermine even formally verified software executing on top. Consequently, ve... » read more

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