Devising Security Solutions For Hardware Threats


Experts At The Table: Hardware security has evolved considerably in recent years, but getting products to market is a challenge in an environment where threats are always evolving and rarely predictable. That’s especially true given the sheer volume and variety of products being introduced. Semiconductor Engineering sat down with a panel of experts at the Design Automation Conference in San F... » read more

Better Security and Power Efficiency of Ascon HW Implementation with STT-MRAM (CEA, et al.)


A new technical paper titled "Enhancing Security and Power Efficiency of Ascon Hardware Implementation with STT-MRAM" was published by researchers at CEA, Leti, Université Grenoble Alpes, CNRS, and Spintec. Abstract "With the outstanding growth of Internet of Things (IoT) devices, security and power efficiency of integrated circuits can no longer be overlooked. Current approved standards f... » read more

Hardware Security: One-Key Premise of Logic Locking


A new technical paper titled "Late Breaking Results: On the One-Key Premise of Logic Locking" was published by researchers at Synopsys. Abstract "The evaluation of logic locking methods has long been predicated on an implicit assumption that only the correct key can unveil the true functionality of a protected circuit. Consequently, a locking technique is deemed secure if it resists a good ... » read more

A HW-Based Correct Execution Environment Supporting Virtual Memory (Korea U., KAIST)


A new technical paper titled "A Hardware-Based Correct Execution Environment Supporting Virtual Memory" was published by researchers at Korea University, Korea Advanced Institute of Science and Technology and other universities. Abstract "The rapid increase in data generation has led to outsourcing computation to cloud service providers, allowing clients to handle large tasks without inve... » read more

Security Technical Paper Roundup: Aug. 27


A number of hardware security-related technical papers were presented at the August 2024 USENIX Security Symposium. The organization provides open access research, and the presentation slides and papers are free to the public. Topics include side-channel attacks and defenses, embedded security, fuzzing, fault injection, logic locking, Rowhammer, and more. Here are some highlights with associate... » read more

Hardware Security Set To Grow Quickly


Experts At The Table: The hardware security ecosystem is young and relatively small but could see a major boom in the coming years. As companies begin to acknowledge how vulnerable their hardware is, industry standards are being set, but must leave room for engineers to experiment. As part of an effort to determine the best way forward, Semiconductor Engineering sat down with a panel of experts... » read more

A Generic Approach For Fuzzing Arbitrary Hypervisors


A technical paper titled “HYPERPILL: Fuzzing for Hypervisor-bugs by Leveraging the Hardware Virtualization Interface” was presented at the August 2024 USENIX Security Symposium by researchers at EPFL, Boston University, and Zhejiang University. Abstract: "The security guarantees of cloud computing depend on the isolation guarantees of the underlying hypervisors. Prior works have presented... » read more

Uncovering A Significant Residual Attack Surface For Cross-Privilege Spectre-V2 Attacks


A technical paper titled “InSpectre Gadget: Inspecting the Residual Attack Surface of Cross-privilege Spectre v2” was presented at the August 2024 USENIX Security Symposium by researchers at Vrije Universiteit Amsterdam. Abstract: "Spectre v2 is one of the most severe transient execution vulnerabilities, as it allows an unprivileged attacker to lure a privileged (e.g., kernel) victim into... » read more

Data Memory-Dependent Prefetchers Pose SW Security Threat By Breaking Cryptographic Implementations


A technical paper titled “GoFetch: Breaking Constant-Time Cryptographic Implementations Using Data Memory-Dependent Prefetchers” was presented at the August 2024 USENIX Security Symposium by researchers at University of Illinois Urbana-Champaign, University of Texas at Austin, Georgia Institute of Technology, University of California Berkeley, University of Washington, and Carnegie Mellon U... » read more

A New Low-Cost HW-Counterbased RowHammer Mitigation Technique


A technical paper titled “ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation” was presented at the August 2024 USENIX Security Symposium by researchers at ETH Zurich. Abstract: "We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation technique that performance-, energy-, and area-efficiently scales with worsening Ro... » read more

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