Cache Occupancy Attacks Targeting The SLC of Apple M-Series SoCs (Northeastern Univ.)


A new technical paper titled "EXAM: Exploiting Exclusive System-Level Cache in Apple M-Series SoCs for Enhanced Cache Occupancy Attacks" was published by researchers at Northeastern University. Abstract "Cache occupancy attacks exploit the shared nature of cache hierarchies to infer a victim's activities by monitoring overall cache usage, unlike access-driven cache attacks that focus on spe... » read more

Benefits Of Memory-Centric Computing (ETH Zurich)


A new technical paper titled "Memory-Centric Computing: Solving Computing's Memory Problem" was published by researchers at ETH Zurich. Abstract "Computing has a huge memory problem. The memory system, consisting of multiple technologies at different levels, is responsible for most of the energy consumption, performance bottlenecks, robustness problems, monetary cost, and hardware real esta... » read more

Hardware Trojan Attack For SNNs (Sorbonne Université, CNRS)


A new technical paper titled "Input-Triggered Hardware Trojan Attack on Spiking Neural Networks" was published by researchers at Sorbonne Universite, CNRS and Queen’s University Belfast. Abstract "Neuromorphic computing based on spiking neural networks (SNNs) is emerging as a promising alternative to traditional artificial neural networks (ANNs), offering unique advantages in terms of low... » read more

On-Chiplet Framework for Verifying Physical Security and Integrity of Adjacent Chiplets


A new technical paper titled "ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification" was published by researchers at Worcester Polytechnic Institute. Abstract "The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller and modular chiplets are integrated onto a singl... » read more

Hardware Security: Assessment Method For Attacks Using Real-World Cases (TU Wien, TÜV Austria)


A new technical paper titled "The Pains of Hardware Security: An Assessment Model of Real-World Hardware Security Attacks" was published by researchers at TU Wien and TÜV Austria. "We review some of the publicly known HW attacks that have occurred and propose an assessment scheme for the attacks and the defense on hardware," states the paper. Find the technical paper here. April 2025. ... » read more

Pre-Silicon Hardware Trojans: Design, Benchmarking, Detection And Prevention (Sandia Labs)


A new technical paper titled "A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans" was published by researchers at Sandia National Laboratories. "In this survey, we first highlight efforts in Trojan design and benchmarking, followed by a cataloging of seminal and recent works in Trojan detection and prevention and their accompanied metrics. Given the volume of l... » read more

Countermeasure Against Confidentiality And Integrity Attacks On Hardware IP (U. of Florida)


A new technical paper titled "HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction" was published by researchers at University of Florida. Abstract "Hardware IP blocks have been subjected to various forms of confidentiality and integrity attacks in recent years due to the globalization of the semiconductor industry. System-on-chip (SoC) designers are now considering a zero... » read more

Auto Sector Leads The Way In IC Security


Concerns about chip and system security are beginning to bear fruit in some markets, driven by the overlap in safety and security in automotive applications and the growing value of algorithms and complex systems in others. But how and when that security is implemented is still all over the map, and so is its effectiveness. The reasons are as nuanced as the designs themselves, which makes it... » read more

LLM-based Agentic Framework Automating HW Security Threat Modeling And Test Plan Generation (U. of Florida)


A new technical paper titled "ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification" was published by researchers at University of Florida. Abstract "Current hardware security verification processes predominantly rely on manual threat modeling and test plan generation, which are labor-intensive, error-prone, and struggle to scale with increasing ... » read more

Multi-Party Computation for Securing Chiplets


A new technical paper titled "Garblet: Multi-party Computation for Protecting Chiplet-based Systems" was published by Worcester Polytechnic Institute. Abstract "The introduction of shared computation architectures assembled from heterogeneous chiplets introduces new security threats. Due to the shared logical and physical resources, an untrusted chiplet can act maliciously to surreptitiousl... » read more

← Older posts Newer posts →