tag: hardware security

HW Security: Pager, Walkie-talkie And Other Battery-Power System Attacks (U. of Florida)
By Technical Paper Link - 31 Jan, 2025 - Comments: 0

A new technical paper titled "When Everyday Devices Become Weapons: A Closer Look at the Pager and Walkie-talkie Attacks" was published by researchers at University of Florida. Abstract "Battery-powered technologies like pagers and walkie-talkies have long been integral to civilian and military operations. However, the potential for such everyday devices to be weaponized has largely been un... » read more

Apple CPU Attacks: SLAP and FLOP (Georgia Tech, Ruhr University Bochum)
By Technical Paper Link - 29 Jan, 2025 - Comments: 0

Two technical papers were published by researchers at Georgia Tech and Ruhr University Bochum detailing CPU side-channel attack vulnerabilities on Apple devices that could reveal confidential data. FLOP: Breaking the Apple M3 CPU via False Load Output Predictions"  Authors: Jason Kim, Jalen Chuang, Daniel Genkin and Yuval Yarom 2025. "We present FLOP, another speculative execution att... » read more

Reverse Engineering Approach for Evaluating HW IP Protection ( U. of Florida, Indiana U.)
By Technical Paper Link - 23 Jan, 2025 - Comments: 0

A technical paper titled "Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection" was published by researchers at University of Florida and Indiana University. Abstract "Existing countermeasures for hardware IP protection, such as obfuscation, camouflaging, and redaction, aim to defend against confidentiality and integrity attacks. However, within the current thr... » read more

Fully Partitioned Security Monitoring Logic From Both The CPU’s Main Core and Privileged SW (KAIST)
By Technical Paper Link - 20 Dec, 2024 - Comments: 0

A new technical paper titled "Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software" was published by researchers at KAIST. The paper states "The existing approaches to instruction trace-based security monitoring hardware are dependent on the privileged software, which presents a signific... » read more

SRAM PUF – The Secure Silicon Fingerprint
By Synopsys - 04 Dec, 2024 - Comments: 0

For many years, silicon Physical Unclonable Functions (PUFs) have been seen as a promising and innovative security technology making steady progress. Today, Static Random-Access Memory (SRAM)-based PUFs have been deployed in hundreds of millions of devices and offer a mature and viable security component that is achieving widespread adoption in commercial products. They are found in devices ran... » read more

98 Hardware Security Failure Scenarios (NIST)
By Technical Paper Link - 03 Dec, 2024 - Comments: 0

A new technical paper titled "Hardware Security Failure Scenarios: Potential Hardware Weaknesses" was published by NIST. Abstract "Hardware is often assumed to be robust from a security perspective. However, chips are both created with software and contain complex encodings (e.g., circuit designs and firmware). This leads to bugs, some of which compromise security. This publication evaluate... » read more

Using Formal For RISC-V Security
By Ed Sperling - 19 Nov, 2024 - Comments: 0

Finding and closing up security holes is becoming more important as chips are used in safety- and mission-critical applications, but it's increasingly important for chips designed for much less costly devices, where the selling price typically doesn't warrant a significant investment in security. The problem is these devices are connected to some of the same networks, and any access points for ... » read more

Systems-in-Package: Authenticated Partial Encryption Protocol For Secure Testing (U. of Florida)
By Technical Paper Link - 12 Nov, 2024 - Comments: 0

A new technical paper titled "GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package" was published by researchers at University of Florida and University of Central Florida. Abstract: "A heterogeneous integrated system in package (SIP) system integrates chiplets outsourced from different vendors into the same substrate for better performance. However, during post-integra... » read more

Effectiveness of Hardware Fuzzing In Detecting Memory Vulnerabilities
By Technical Paper Link - 08 Nov, 2024 - Comments: 0

A new technical paper titled "Fuzzerfly Effect: Hardware Fuzzing for Memory Safety" was published by researchers at Technical University of Darmstadt, Texas A&M University and Delft University of Technology. Abstract: "Hardware-level memory vulnerabilities severely threaten computing systems. However, hardware patching is inefficient or difficult post-fabrication. We investigate the eff... » read more

Democratizing Roots of Trust from Silicon to Software
By Synopsys - 07 Nov, 2024 - Comments: 0

With a vast amount of devices getting connected to the Internet of Things (IoT) and the growing number of low-cost attacks being developed to hack such IoT devices, it is clear that the need for embedded security solutions is rising dramatically. A security subsystem in the main system-on-chip (SoC) of a device can be deployed to offer secure cryptographic services to the applications running o... » read more

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