tag: hardware security

Modeling and Testing Microarchitectural Leakage of CPU Exceptions (Microsoft, Vrije Universiteit Amsterdam)
By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A new technical paper titled "Speculation at Fault: Modeling and Testing Microarchitectural Leakage of CPU Exceptions" was published by researchers at Microsoft and Vrije Universiteit Amsterdam. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "Microarchitectural leakage models provide effective tools to prevent vulnerabilities such as Spectre and Meltdown vi... » read more

Microarchitectural Side-Channel Attacks And Defenses on NVRAM DIMMs
By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A new technical paper titled "NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems" was published by researchers at UC San Diego, Purdue University, and UT Austin. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "We study microarchitectural side-channel attacks and defenses on non-volatile RAM (NVRAM) DIMMs. In this study, we first perform r... » read more

Formal Processor Model Providing Provably Secure Speculation For The Constant-Time Policy
By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A new technical paper titled "ProSpeCT: Provably Secure Speculation for the Constant-Time Policy" was published by researchers at imec-DistriNet, KU Leuven, CEA, and INRIA. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "We propose ProSpeCT, a generic formal processor model providing provably secure speculation for the constant-time policy. For constant-tim... » read more

How Attackers Can Read Data From CPU’s Memory By Analyzing Energy Consumption
By Technical Paper Link - 07 Aug, 2023 - Comments: 0

A technical paper titled “Collide+Power: Leaking Inaccessible Data with Software-based Power Side Channels” was published by researchers at Graz University of Technology and CISPA Helmholtz Center for Information Security. Abstract: "Differential Power Analysis (DPA) measures single-bit differences between data values used in computer systems by statistical analysis of power traces. In th... » read more

Programmable HW Accelerators For BGV Fully Homomorphic Encryption In The Cloud
By Technical Paper Link - 02 Aug, 2023 - Comments: 0

A technical paper titled “BASALISC: Programmable Hardware Accelerator for BGV Fully Homomorphic Encryption” was published by researchers at COSIC KU Leuven, Galois Inc., and Niobium Microsystems. Abstract: "Fully Homomorphic Encryption (FHE) allows for secure computation on encrypted data. Unfortunately, huge memory size, computational cost and bandwidth requirements limit its practic... » read more

Heat-Tolerant CNT-Based PUFs
By Technical Paper Link - 28 Jul, 2023 - Comments: 0

A technical paper titled “CNT-PUFs: Highly Robust and Heat-Tolerant Carbon-Nanotube-Based Physical Unclonable Functions for Stable Key Generation” was published by researchers at Chemnitz University of Technology, University of Passau, Technical University of Darmstadt, and Fraunhofer Institute for Electronic Nano Systems (ENAS). Abstract: "In this work, we explore a highly robust and... » read more

NoC Obfuscation For Protecting Against Reverse Engineering Attacks (U. Of Florida)
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks" was published by researchers at University of Florida. Abstract: "Modern System-on-Chip designs typically use Network-on-Chip (NoC) fabrics to implement coordination among integrated hardware blocks. An important class of security vulnerabilities involves a rogue foundry reverse-engineeri... » read more

RowPress: Read-Disturb Phenomenon In DDR4 DRAM Chips
By Technical Paper Link - 15 Jul, 2023 - Comments: 0

A technical paper titled "RowPress: Amplifying Read Disturbance in Modern DRAM Chips" was published by researchers at ETH Zürich. Abstract: "Memory isolation is critical for system reliability, security, and safety. Unfortunately, read disturbance can break memory isolation in modern DRAM chips. For example, RowHammer is a well-studied read-disturb phenomenon where repeatedly opening and clo... » read more

Hardware-Efficient Approach To Defend Against Fault Attacks
By Technical Paper Link - 13 Jul, 2023 - Comments: 0

A technical paper titled "Fault Attacks on Access Control in Processors: Threat, Formal Analysis and Microarchitectural Mitigation" was published by researchers at University of Kaiserslautern-Landau. Abstract: "Process isolation is a key component of the security architecture in any hardware/software system. However, even when implemented correctly and comprehensively at the software (SW) le... » read more

How Voltage-Controlled MRAM Devices Can Be Used To Create Unique Fingerprints Of Microelectronic Chips
By Technical Paper Link - 08 Jul, 2023 - Comments: 0

A technical paper titled "Reconfigurable Physically Unclonable Functions Based on Nanoscale Voltage-Controlled Magnetic Tunnel Junctions" was published by researchers at Northwestern University, Western Digital Corporation, Fe Research Inc., and University of Messina. Abstract: "With the fast growth of the number of electronic devices on the internet of things (IoT), hardware-based securi... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy