NVIDIA GPU Confidential Computing: Threat Model And Security Insights (IBM Research, Ohio State)


A new technical paper titled "NVIDIA GPU Confidential Computing Demystified" was published by IBM Research and Ohio State University. Abstract "GPU Confidential Computing (GPU-CC) was introduced as part of the NVIDIA Hopper Architecture, extending the trust boundary beyond traditional CPU-based confidential computing. This innovation enables GPUs to securely process AI workloads, providing ... » read more

Functional Hardware Trojans Specifically Tailored Tor SFQ (Univ. of Rochester)


A new technical paper titled "Hardware trojans in superconducting electronic circuits" was published by researchers at University of Rochester. Abstract "Hardware Trojans that exploit the unique characteristics of superconducting electronic (SCE) circuits are explored in this paper. Two types of hardware Trojan circuits are proposed: a magnetically-coupled data transmission Trojan embedded ... » read more

HW Security: A Hybrid Verification Method Combining Simulation And Formal Verification (RPTU, UCSD)


A new technical paper titled "FastPath: A Hybrid Approach for Efficient Hardware Security Verification" was published by researchers at RPTU Kaiserslautern-Landau and UC San Diego. "We propose FastPath, a hybrid verification methodology that combines the efficiency of simulation with the exhaustive nature of formal verification. FastPath employs a structural analysis framework to automate th... » read more

GNN-Based Framework for Hardware Trojan Detection, Including RISC-V Cores


A new technical paper titled "TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs" was published by researchers at University of Connecticut and University of Minnesota. Abstract "hip manufacturing is a complex process, and to achieve a faster time to market, an increasing number of untrusted third-party tools and designs from around the world are being utilized. The use of th... » read more

HW Security: Multi-Agent AI Assistant Leveraging LLMs To Automate Key Stages of SoC Security Verification (U. of Florida)


A new technical paper titled "SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models" was published by researchers at University of Florida. Abstract "Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenges in automation, scalability, c... » read more

Metrics And Methodology for Hardware Security Constructs (NIST)


A new technical paper titled "Metrics and Methodology for Hardware Security Constructs" was published by NIST. Abstract "Although hardware is commonly believed to be security-resilient, it is often susceptible to vulnerabilities arising from design and implementation flaws. These flaws have the potential to jeopardize not only the hardware's security, but also its operations and critical us... » read more

V-NAND PUFs (Seoul National University, SK hynix)


A new technical paper titled "Concealable physical unclonable functions using vertical NAND flash memory" was published by researchers at Seoul National University and SK hynix. The paper proposes "a concealable PUF using V-NAND flash memory by generating PUF data through weak Gate-Induced-Drain-Leakage (GIDL) erase." Find the technical paper here. June 2025. Park, SH., Koo, RH., Yang,... » read more

Air-Gap Covert Channel Attack On Spread Spectrum Modulated Clocks (IETR, Lab-STICC)


A new technical paper titled "Clock-to-Clock Modulation Covert Channel" was published by researchers at University of Rennes-INSA Rennes-IETR-UMR  and University of South Brittany/Lab-STICC- UMR CNRS. Abstract "Various Electromagnetic (EM) attacks have been developed to modulate and utilize EM emanations for covert communication, including exploiting processors, memory modules, and periphe... » read more

Cache Side-Channel Attacks On LLMs (MITRE, WPI)


A new technical paper titled "Spill The Beans: Exploiting CPU Cache Side-Channels to Leak Tokens from Large Language Models" was published by researchers at MITRE and Worcester Polytechnic Institute. Abstract "Side-channel attacks on shared hardware resources increasingly threaten confidentiality, especially with the rise of Large Language Models (LLMs). In this work, we introduce Spill The... » read more

Cache Occupancy Attacks Targeting The SLC of Apple M-Series SoCs (Northeastern Univ.)


A new technical paper titled "EXAM: Exploiting Exclusive System-Level Cache in Apple M-Series SoCs for Enhanced Cache Occupancy Attacks" was published by researchers at Northeastern University. Abstract "Cache occupancy attacks exploit the shared nature of cache hierarchies to infer a victim's activities by monitoring overall cache usage, unlike access-driven cache attacks that focus on spe... » read more

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