tag: hardware-software co-design

An Agent-Driven End-to-End HW-SW Co-Design Benchmark for Heterogeneous SoCs (Columbia, IBM)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Columbia University and IBM Research have released “HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip”. Abstract “Large language models (LLMs) are adopted for software and hardware design, yet these domains are still evaluated separately. Software benchmarks typically assume fixed hardware targets, while hardware be... » read more

10-Year Roadmap for AI + Hardware (UIUC, UCLA, Stanford et al.)
By Technical Paper Link - 06 Mar, 2026 - Comments: 0

Researchers from University of Illinois Urbana-Champaign, UCLA, Stanford University, Nvidia, Google, et al. have released “AI+HW 2035: Shaping the Next Decade”. Abstract “Artificial intelligence (AI) and hardware (HW) are advancing at unprecedented rates, yet their trajectories have become inseparably intertwined. The global research community lacks a cohesive, long-term vision t... » read more

Optimizing In-Memory AI Accelerators Across Multiple Workloads (KAUST, Compumacy)
By Technical Paper Link - 06 Mar, 2026 - Comments: 0

Researchers from KAUST and Compumacy for Artificial Intelligence Solutions have released “Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators”. Abstract “Software-hardware co-design is essential for optimizing in-memory computing (IMC) hardware accelerators for neural networks. However, most existing optimization frameworks target a single workload, lea... » read more

HW-Accelerated Physical AI Framework For Resource-Constrained Edge Devices (ASU)
By Technical Paper Link - 07 Jan, 2026 - Comments: 0

A new technical paper titled "Enabling Physical AI at the Edge: Hardware-Accelerated Recovery of System Dynamics" was published by researchers at Arizona State University. Abstract "Physical AI at the edge—enabling autonomous systems to understand and predict real-world dynamics in realtime—demands efficient hardware acceleration. Model recovery (MR), which extracts governing equations ... » read more

Accelerator Architecture For In-Memory Computation of CNN Inferences Using Racetrack Memory
By Technical Paper Link - 03 Jul, 2025 - Comments: 0

A new technical paper titled "Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems" was published by researchers at National University of Singapore, A*STAR, Chinese Academy of Sciences, and Hong Kong University of Science and Technology. Abstract "Deep neural networks generate and process large volumes of data, posing challe... » read more

A Novel Approach For HW/SW Co-Verification
By Siemens EDA - 27 Mar, 2025 - Comments: 0

The complexity of system on chips (SoCs) continues to grow rapidly. Accordingly, new standards and methodologies are introduced to overcome these verification challenges. The Portable Test and Stimulus Standard (PSS) from Accellera is one of the standard examples used to pursue such challenges. In this paper we will show a methodology to use PSS to orchestrate the process of HW/SW co-verificati... » read more

Where Is The Software For Shift Left?
By Brian Bailey - 12 Dec, 2024 - Comments: 0

Co-development of hardware and software has been a dream for a long time, but significant hurdles remain. Neither domain is ready with what the other requires at the appropriate time. The earlier something can be done in a development flow, the less likely problems will be found when they are more difficult or expensive to fix. It may require both tool and methodology changes, so that a proc... » read more

Toward Software-Defined Vehicles
By Ed Sperling - 24 Jul, 2024 - Comments: 0

Speed is everything when it comes to designing automotive electronics, but not in the usual way. In the past, product cycles often lasted five to seven years, from initial design to implementation inside of vehicles. That no longer works as vehicles adopt more electronic features to replace mechanical ones, and as competition heats up over the latest features and nearly instantaneous over-the-a... » read more

New Memory Architecture For Local Differential Privacy in Hardware
By Technical Paper Link - 02 Apr, 2024 - Comments: 0

A technical paper titled "Two Birds with One Stone: Differential Privacy by Low-power SRAM Memory" was published by researchers at North Carolina State University, University of South Alabama, and University of Tennessee. Abstract "The software-based implementation of differential privacy mechanisms has been shown to be neither friendly for lightweight devices nor secure against side-channe... » read more

Optimizing Energy At The System Level
By Brian Bailey - 18 Mar, 2024 - Comments: 0

Power is a ubiquitous concern, and it is impossible to optimize a system's energy consumption without considering the system as a whole. Tremendous strides have been made in the optimization of a hardware implementation, but that is no longer enough. The complete system must be optimized. There are far reaching implications to this, some of which are driving the path toward domain-specific c... » read more

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