tag: hardware-software co-design

Simplifying AI Edge Deployment
By Ed Sperling - 10 Oct, 2022 - Comments: 0

Barrie Mullins, vice president of product at Flex Logix, explains how a programmable accelerator chip can simplify semiconductor design at the edge, where chips need to be high performance as well as low power, yet developing everything from scratch is too expensive and time-consuming. Programmability allows these systems to stay current with changes in algorithms, which can affect everything f... » read more

Algorithm HW Framework That Minimizes Accuracy Degradation, Data Movement, And Energy Consumption Of DNN Accelerators (Georgia Tech)
By Technical Paper Link - 31 Aug, 2022 - Comments: 0

This new research paper titled "An Algorithm-Hardware Co-design Framework to Overcome Imperfections of Mixed-signal DNN Accelerators" was published by researchers at Georgia Tech. According to the paper's abstract, "In recent years, processing in memory (PIM) based mixed-signal designs have been proposed as energy- and area-efficient solutions with ultra high throughput to accelerate DNN com... » read more

Polynesia, A Novel Hardware/Software Cooperative Design for In-Memory HTAP Databases
By Technical Paper Link - 22 Aug, 2022 - Comments: 0

A team of researchers from ETH Zurich, Google and Univ. of Illinois Urbana-Champaign recently published a technical paper titled "Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design". Abstract (partial) "We propose Polynesia, a hardware–software co-designed system for in-memory HTAP [hybrid transactional/anal... » read more

HW/SW Co-Design to Configure DNN Models On Energy Harvesting Devices
By Technical Paper Link - 20 Jul, 2022 - Comments: 0

New technical paper titled "EVE: Environmental Adaptive Neural Network Models for Low-Power Energy Harvesting System" was published by researchers at UT San Antonio, University of Connecticut, and Lehigh University. According to the abstract: "This paper proposes EVE, an automated machine learning (autoML) co-exploration framework to search for desired multi-models with shared weights for... » read more

The Challenge Of Optimizing Chip Architectures For Workloads
By Brian Bailey - 12 May, 2022 - Comments: 1

It isn't possible to optimize a workload running on a system just by looking at hardware or software separately. They need to be developed together and intricately intertwined, an engineering feat that also requires bridging two worlds with have a long history of operating independently. In the early days of computing, hardware and software were designed and built by completely separate team... » read more

Domain-Specific Design Drives EDA Changes
By Ann Mutschler - 03 Jan, 2022 - Comments: 0

The chip design ecosystem is beginning to pivot toward domain-specific architectures, setting off a scramble among tools vendors to simplify and optimize existing tools and methodologies. The move reflects a sharp slowdown in Moore's Law scaling as the best approach for improving performance and reducing power. In its place, chipmakers — which now includes systems companies — are pushing... » read more

Continuous Integration For Digital Design
By Christian Skubich - 17 Dec, 2021 - Comments: 0

By Christian Skubich and Nico Peter In 2001, the Manifesto for Agile Software Development [1] laid the foundation for many modern software development processes. Today, 20 years later, agile methods are in widespread use in numerous domains. Out of the participants in the study Status Quo (Scaled) Agile 2020 [2], only 9% still relied on classic project management methods. One core element... » read more

Designing Low Energy Chips And Systems
By Ann Mutschler - 01 Feb, 2021 - Comments: 1

Energy optimization is beginning to shift left as design teams begin examining new ways to boost the performance of devices without impacting battery life or ratcheting up electricity costs. Unlike power optimization, where a skilled engineering team may reduce power by 1% to 5%, energy efficiency may be able to cut effective power in half. But those gains require a significant rethinking of... » read more

Hidden Costs In Faster, Low-Power AI Systems
By Ed Sperling - 20 Jan, 2021 - Comments: 1

Chipmakers are building orders of magnitude better performance and energy efficiency into smart devices, but to achieve those goals they also are making tradeoffs that will have far-reaching, long-lasting, and in some cases unknown impacts. Much of this activity is a direct result of pushing intelligence out to the edge, where it is needed to process, sort, and manage massive increases in da... » read more

Power Models For Machine Learning
By Brian Bailey - 14 Dec, 2020 - Comments: 1

AI and machine learning are being designed into just about everything, but the chip industry lacks sufficient tools to gauge how much power and energy an algorithm is using when it runs on a particular hardware platform. The missing information is a serious limiter for energy-sensitive devices. As the old maxim goes, you can't optimize what you can't measure. Today, the focus is on functiona... » read more

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