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Domain-Specific Design Drives EDA Changes


The chip design ecosystem is beginning to pivot toward domain-specific architectures, setting off a scramble among tools vendors to simplify and optimize existing tools and methodologies. The move reflects a sharp slowdown in Moore's Law scaling as the best approach for improving performance and reducing power. In its place, chipmakers — which now includes systems companies — are pushing... » read more

Continuous Integration For Digital Design


By Christian Skubich and Nico Peter In 2001, the Manifesto for Agile Software Development [1] laid the foundation for many modern software development processes. Today, 20 years later, agile methods are in widespread use in numerous domains. Out of the participants in the study Status Quo (Scaled) Agile 2020 [2], only 9% still relied on classic project management methods. One core element... » read more

Designing Low Energy Chips And Systems


Energy optimization is beginning to shift left as design teams begin examining new ways to boost the performance of devices without impacting battery life or ratcheting up electricity costs. Unlike power optimization, where a skilled engineering team may reduce power by 1% to 5%, energy efficiency may be able to cut effective power in half. But those gains require a significant rethinking of... » read more

Hidden Costs In Faster, Low-Power AI Systems


Chipmakers are building orders of magnitude better performance and energy efficiency into smart devices, but to achieve those goals they also are making tradeoffs that will have far-reaching, long-lasting, and in some cases unknown impacts. Much of this activity is a direct result of pushing intelligence out to the edge, where it is needed to process, sort, and manage massive increases in da... » read more

Power Models For Machine Learning


AI and machine learning are being designed into just about everything, but the chip industry lacks sufficient tools to gauge how much power and energy an algorithm is using when it runs on a particular hardware platform. The missing information is a serious limiter for energy-sensitive devices. As the old maxim goes, you can't optimize what you can't measure. Today, the focus is on functiona... » read more

Silicon Lifecycle Management


How do you track, measure and ensure reliability over the lifetime of a chip, regardless of how or where it is used? Steve Pateras, senior director of marketing for test products at Synopsys, drills down into the impact of hardware-software co-design, over-the-air updates, the expected lifetime of designs, and how the various monitors and sensors are used to track environmental, structural and ... » read more

Faster Inferencing At The Edge


Cheng Wang, senior vice president of engineering at Flex Logix, talks about inferencing at the edge, what are some of the main considerations in designing and choosing an inferencing chip, why programmability and modularity are important, and how hardware-software co-design with algorithms can improve performance and power. » read more

Getting Particular About Partitioning


Partitioning could well be one of the most important and pervasive trends since the invention of computers. It has been around for almost as long, too. The idea dates back at least as far back as the Manhattan Project during World War II, when computations were wrapped within computations. It continued from there with what we know as time-sharing, which rather crudely partitioned access by p... » read more

Customization And Limitations At The Edge


Semiconductor Engineering sat down to discuss the edge constraints and the need for security with Jeff DeAngelis, managing director of the Industrial and Healthcare Business Unit at Maxim Integrated; Norman Chang, chief technologist at Ansys; Andrew Grant, senior director of artificial intelligence at Imagination Technologies; Thomas Ensergueix, senior director of the automotive and IoT line of... » read more

Rethinking Architectures Based On Power


The newest chips being developed for everything from the cloud to the edge of the network look nothing like designs of even a year or two ago. They are architected for speed, from the throughput of high-speed buses and external interconnects to the customized accelerators and arrays of redundant MACs. But many of these designs have barely scratched the surface for saving power, which will becom... » read more

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