Algorithm HW Framework That Minimizes Accuracy Degradation, Data Movement, And Energy Consumption Of DNN Accelerators (Georgia Tech)


This new research paper titled “An Algorithm-Hardware Co-design Framework to Overcome Imperfections of Mixed-signal DNN Accelerators” was published by researchers at Georgia Tech.

According to the paper’s abstract, “In recent years, processing in memory (PIM) based mixed-signal designs have been proposed as energy- and area-efficient solutions with ultra high throughput to accelerate DNN computations. However, PIM designs are sensitive to imperfections such as noise, weight and conductance variations that substantially degrade the DNN accuracy. To address this issue, we propose a novel algorithm-hardware co-design framework hereafter referred to as HybridAC that simultaneously avoids accuracy degradation due to imperfections, improves area utilization, and reduces data movement and energy dissipation.”

Find the technical paper here. Published August 2022.

Authors: Payman Behnam, Uday Kamal, Saibal Mukhopadhyay.

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