CSR Management: Life Beyond Spreadsheets


The ASIC, ASSP, and system-on-chip (SoC) design landscape has undergone significant evolution over the past two decades. For example, while early devices contained only tens of intellectual property (IP) blocks, modern high-end SoCs may integrate up to 1000 IPs, each containing millions of logic gates. Furthermore, unlike their predecessors, today’s SoCs are no longer primarily hardware; i... » read more

Modernizing The Hardware / Software Interface – Life Beyond Spreadsheets


The hardware/software interface (HSI) is the core of advanced semiconductor design, allowing seamless interaction between software and components like accelerators and peripherals. It underpins critical functions such as documentation, firmware, and hardware verification. Inefficient or outdated HSI management reduces collaboration, increases design errors, and threatens the performance and qua... » read more

System-on-Chip Integration Complexity And Hardware/Software Contracts


From the earliest days of my career, when designing chips, I have always navigated the interface between hardware and software for semiconductor design in my roles. My initial chip designs included video and audio encoding and decoding, supporting standards like MPEG and H.261. As acceleration parts of hardware/software systems, these had many Control and Status Registers (CSRs) to program. The... » read more

Using Automotive IP For Easier Integration Of Safety Into SoCs


By Shivakumar Chonnad and Vladimir Litovtchenko Today’s SoCs for automotive safety-related systems integrate numerous IP blocks. At the system level, the Hardware Software Interface (HSI) between these IP blocks needs to be verified in simulation and validated in prototype. However, the scaling of the scope and effort to verify or validate is not linear based on the growing complexity of S... » read more

Portable Test and Stimulus Standard Version 1.0


The definition of the language syntax, C++ library API, and accompanying semantics for the specification of verification intent and behaviors reusable across multiple target platforms and allowing for the automation of test generation is provided. This standard provides a declarative environment designed for abstract behavioral description using actions, their inputs, outputs, and resource depe... » read more