tag: HBM2

The Week In Review: Design
By Jesse Allen - 28 Jul, 2017 - Comments: 0

IP Synopsys unveiled High Bandwidth Memory 2 (HBM2) IP. The package includes PHY, controller and verification IP and supports data rates up to 2400Mb/s, 20% faster than the JEDEC standard specification. The controller supports pseudo-channel operation in either lock step or memory interleaved mode, and the PHY offers four trained power management states and fast frequency switching. Cadence... » read more

Optimal Memory Strategies: Where HBM2 Fits
By eSilicon - 23 Mar, 2017 - Comments: 0

How are you going to build your next big product? Whether it’s in the networking, wireless, mobile or computing market, you are now increasing the functionality of your product. It needs to be able to do many tasks – fast, at low power, and pack as much functionality into the tiniest area for cost effectiveness. What does this mean for the embedded memory content? It is growing rapidly. ... » read more

HBM2: It’s All About The PHY
By Bill Fuller - 09 Mar, 2017 - Comments: 0

HBM DRAM is currently used in graphics, high-performance computing (HPC), server, networking and client applications. HBM, says JEDEC HBM Task Group Chairman Barry Wagner, provides a “compelling solution” to reduce the IO power and memory footprint for the most demanding applications. Recent examples of second-generation HBM deployment include NVIDIA’s Quadro GP100 GPU which is paired wit... » read more

The Challenges Of Designing An HBM2 PHY
By Frank Ferro - 09 Feb, 2017 - Comments: 1

Originally targeted at the graphics industry, HBM continues to gain momentum in the server and networking markets as system designers work to move higher bandwidth closer to the CPU. Expanding DRAM capacity – which boosts overall system performance – allows data centers to maximize local DRAM storage for wide throughput. HBM DRAM architecture effectively increases system memory bandwidth... » read more

What’s Missing In Advanced Packaging
By Ann Mutschler - 22 Dec, 2016 - Comments: 0

Even though Moore's Law is running out of steam, there is still a need to increase functional density. Increasingly, this is being done with heterogeneous integration at the package or module level. This is proving harder than it looks. At this point there are no standardized methodologies, and tools often are retrofitted versions of existing tools that don't take into account the challenges... » read more

Partitioning For Power
By Ed Sperling - 14 Nov, 2016 - Comments: 0

Examine any smartphone design today and most of the electronic circuitry is "off" most of the time. And regardless of how many processor cores are available, it's rare to use more than a couple of those cores at any point in time. The emphasis is shifting, though, as the mobility market flattens and other markets such as driver-assisted vehicles and IoT begin gaining traction. In a car, turn... » read more

New Memory Approaches And Issues
By Ed Sperling - 14 Mar, 2016 - Comments: 1

New memory types and approaches are being developed and tested as DRAM and Moore's Law both run out of steam, adding greatly to the confusion of what comes next and how that will affect chip designs. What fits where in the memory hierarchy is becoming less clear as the semiconductor industry grapples with these changes. New architectures, such as [getkc id="202" kc_name="fan-outs"] and [getk... » read more

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