tag: Helic

Electromagnetic Analysis and Signoff: Cost Savings
By Magdy Abadir - 18 Sep, 2018 - Comments: 0

By Nikolas Provatas and Magdy Abadir We are often asked by SoC design teams about the benefits of an electromagnetic analysis and signoff methodology. Here is an overview of some of the big “cost savings”. Time to Market Savings Utilizing an EM crosstalk analysis and signoff methodology provides designers with an “insurance policy” against the risk of EM coupling in their SOC des... » read more

Aging In Advanced Nodes
By Ann Mutschler - 17 Sep, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; Magdy Abadir, vice president of marketing at ... » read more

Enabling Cheaper Design
By Brian Bailey - 13 Sep, 2018 - Comments: 1

While the EDA industry tends to focus on cutting edge designs, where design costs are a minor portion of the total cost of product, the electronics industry has a very long tail. The further along the tail you go, the more significant design costs become as a percent of total cost. Many of those designs are traditionally built using standard parts, such as microcontrollers, but as additional... » read more

Process Corner Explosion
By Ann Mutschler - 13 Sep, 2018 - Comments: 1

The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

The Rising Cost Of 5G
By Ed Sperling - 22 Aug, 2018 - Comments: 0

Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

Minimizing The Risk Of Electromagnetic Crosstalk Failures
By Magdy Abadir - 09 Aug, 2018 - Comments: 0

Leading semiconductor markets, such automotive, machine learning, large scale computing and networking, are driving the need for high density chips that integrate high performance digital cores with sensitive analog/RF IP, while operating at the lowest power and fastest bandwidth possible. These trends are increasing the sensitivity to electromagnetic (EM) coupling, and requiring designers to w... » read more

Taking Inductance And Electromagnetic Effects More Seriously
By Magdy Abadir - 03 Aug, 2018 - Comments: 0

By Magdy Abadir and Yehea Ismail With increasing frequencies, tighter margins, denser integrated circuits, new devices and materials, the necessity of full EM analysis including magnetic/inductive effects is becoming a fundamental question for the industry. Where and when should full EM verification be included? Can some of major chip failures during development be attributed to ignoring ... » read more

New 5G Hurdles
By Ed Sperling - 01 Aug, 2018 - Comments: 1

Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

Safety, Security And PPA Tradeoffs
By Brian Bailey - 23 Jul, 2018 - Comments: 0

Safety and security are emerging as key design tradeoffs as chips are added into safety-critical markets, adding even more complexity into an already complicated optimization process. In the early days of semiconductor design, performance and area were traded off against each other. Then power became important, and the main tradeoffs became power, performance and area (PPA). But as chips inc... » read more

Week In Review: Design, Low Power
By Jesse Allen - 20 Jul, 2018 - Comments: 0

Aldec expanded the rule-checking capabilities of its ALINT-PRO tool, adding twice as many FSM checks and new graphical representations to aid state exploration. Also included is enhanced setup automation for complex Xilinx Vivado and ISE projects that automatically organizes a workspace to deliver hierarchical and incremental DRC and CDC analysis. Xilinx acquired AI startup DeePhi Technology... » read more

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