tag: heterogeneous integration

ECTC 2024 Session Readout: Advancement of Metrology
By Technical Paper Link - 04 Sep, 2024 - Comments: 0

A Electronic Components and Technology Conference (ECTC) session report titled "2024 ECTC Special Session Report: Advancing Metrology for Next-Generation Microelectronics" was published by NIST, Binghamton University, and TechSearch International. Abstract: "Metrology plays a pivotal role in semiconductor research, manufacturing, packaging and assembly. It is critical to the success of this... » read more

Defining The Chiplet Socket
By Brian Bailey - 29 Aug, 2024 - Comments: 0

Experts At The Table: The semiconductor industry has been buzzing with the possibilities surrounding chiplets, but so far this packaging technology has been confined to large semiconductor companies that are vertically integrated. The industry has been attempting to open this up to a broader group of people. To work out what this means for chiplets, and what standardization will be required, Se... » read more

3.5D: The Great Compromise
By Ed Sperling - 21 Aug, 2024 - Comments: 1

The semiconductor industry is converging on 3.5D as the next best option in advanced packaging, a hybrid approach that includes stacking logic chiplets and bonding them separately to a substrate shared by other components. This assembly model satisfies the need for big increases in performance while sidestepping some of the thorniest issues in heterogeneous integration. It establishes a midd... » read more

Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding
By Brewer Science - 23 Jul, 2024 - Comments: 0

A technical paper titled "Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding" was published by researchers at imec, Brewer Science and SUSS MicroTec Lithography GmbH. Abstract "A collective die-to-wafer bonding flow is extended beyond the N=2 tier to the N=3 and N=4 tier by collectively bonding multiple layers of dies on top of a target wafer. The N=2 die-level is show... » read more

X-ray Inspection Becoming Essential In Advanced Packaging
By Gregory Haley - 09 Jul, 2024 - Comments: 0

X-ray technology is moving into the mainstream of chip manufacturing as complex assemblies and advanced packaging make it increasingly difficult to ensure these devices will work as expected throughout their lifecycles. A single defect in a chiplet or interconnect can transform a complex advanced package into expensive scrap, and the risk only increases as the chip industry shifts from homog... » read more

Controlling Warpage In Advanced Packages
By Laura Peters - 24 Jun, 2024 - Comments: 1

Warpage is becoming a serious concern in advanced packaging, where a heterogeneous mix of materials can cause uneven stress points during assembly and packaging, and under real workloads in the field. Warpage plays a critical role in determining whether an advanced package can be assembled successfully and meet long-term reliability targets. New advances, such as molding compounds with impro... » read more

Promises And Pitfalls Of SoC Restructuring
By Ed Sperling - 12 Jun, 2024 - Comments: 0

As chips become more complex and increasingly heterogeneous, it's becoming more difficult to keep track of different methodologies, tools, and blend data from different sources to create a chip. Tim Schneider, staff application engineer at Arteris, explains why IP-XACT has become so critical, why it took so long to gain a solid foothold in chip design, and how the new IP-XACT standard interface... » read more

Integration Hurdles For Analog And RF In Next-Gen Packages
By Gregory Haley - 23 May, 2024 - Comments: 0

A rapid increase in wireless connectivity and more sensors, coupled with a shift away from monolithic SoCs toward heterogeneous integration, is driving up the amount of analog/RF content in systems and changing the dynamics within a package. Since the early 2000s, the majority of chips used at the most advanced nodes were systems-on-chip (SoCs). All features had to fit into a single planar S... » read more

Secure Movement Of Data In Test
By Ed Sperling - 16 Apr, 2024 - Comments: 0

Historically, test data flowed out of the tester and was loaded into a file. But with heterogeneous integration, including chiplets and IP from multiple vendors, test data is now being streamed across the manufacturing floor where it can be used to make real-time decisions. Eli Roth, product manager for smart manufacturing at Teradyne, talks with Semiconductor Engineering about challenges in da... » read more

Challenges With Chiplets And Power Delivery
By Ed Sperling - 15 Apr, 2024 - Comments: 0

Chiplets hold the potential to deliver the same PPA benefits as an SoC, but with many more features and options that are possible on a reticle-constrained die. If chiplets live up to the hype, they will deliver what is essentially mass customization, democratizing and speeding the delivery of complex chips across a broad array of markets. Today, the focus has been on die-to-die interfaces, but ... » read more

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