tag: heterogeneous integration

3D-IC Success Stories: Faster Bandwidth, Lower Power, On-Time Tapeouts
By Reela Samuel - 08 Jan, 2026 - Comments: 0

As scaling at advanced nodes becomes increasingly constrained by cost, yield, and power density, semiconductor innovation is shifting decisively toward 3D-IC technologies, chiplets, and heterogeneous integration. Across AI infrastructure, cloud computing, automotive electronics, and high-performance systems, design teams are moving beyond monolithic SoCs to unlock new levels of performance, e... » read more

Chip Industry’s Top Videos 2025
By The SE Staff - 30 Dec, 2025 - Comments: 0

Rising complexity, new architectures, and AI's permeation of nearly everything left engineers struggling to keep up in 2025, as evidenced by this year's viewership numbers. Among the hottest topics were verification, agentic AI, DRAM/HBM, optimization of data movement, chiplets, and heterogeneous integration, but there was steady traffic growth across all sectors. Top 10 most-watched videos ... » read more

When To Move To Multi-Die Assemblies
By Ann Mutschler - 23 Dec, 2025 - Comments: 0

As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

Simplifying ESD Protection and Inter-Chiplet Signaling In Future 2.5D/3D Packaging Technologies (Arizona State, Univ. of Minnesota)
By Technical Paper Link - 25 Nov, 2025 - Comments: 0

A new technical paper titled "Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity" was published by researchers at Arizona State University and University of Minnesota. Abstract: "The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction... » read more

Enabling The Future: Heterogeneous Integration From Connected Devices To Data Centers
By WonChul Do - 23 Oct, 2025 - Comments: 0

The digital landscape is evolving at an unprecedented pace. From smartphones and wearables to autonomous vehicles and hyperscale data centers, the demand for faster, smarter, and more efficient electronics is reshaping the semiconductor industry. At the core of this transformation is heterogeneous integration—the convergence of multiple technologies, functions, and components into unified sys... » read more

Microelectronics and Advanced Packaging Technologies Roadmap 2.0 (SRC)
By Technical Paper Link - 14 Oct, 2025 - Comments: 0

The Semiconductor Research Corporation just released its Microelectronics and Advanced Packaging Technologies (MAPT) Roadmap 2.0, a comprehensive update to the industry’s first 3D semiconductor roadmap. The roadmap includes contributions of over 370 experts from 132 organizations, with updated content and a new chapter on digital twins and their applications. The roadmap was funded by the ... » read more

Critical Challenges and Opportunities Related to Polymer-Based Materials in Semiconductor Packaging (NIST, NC State, NREL et al)
By Technical Paper Link - 11 Sep, 2025 - Comments: 0

A new technical paper titled "Material Needs and Measurement Challenges for Advanced Semiconductor Packaging: Understanding the Soft Side of Science" was published by researchers at the National Institute of Standards and Technology, North Carolina State University, National Renewable Energy Laboratory, ASE, Intel, Innocentrix, and Binghamton University. Abstract "This Perspective builds up... » read more

The Need for System-Technology Co-Optimization (STCO)
By Benjamin Prautsch - 11 Sep, 2025 - Comments: 0

Modern semiconductor components are becoming more and more complex and cost sensitive. To master technological and economic challenges, new chiplet approaches and heterogeneous integration technologies are becoming increasingly relevant. This, in turn, calls for new heterogeneous design approaches. They make it possible to combine different design domains across technological options while sati... » read more

Chiplet Design Considerations
By Robert Kruger - 28 Aug, 2025 - Comments: 0

Chiplets are a way to offer continuing increases in compute capacity and I/O bandwidth needs by splitting SoC functionality into smaller heterogeneous or homogeneous dies called chiplets and integrating these chiplets into a single system in package (SIP), where the total silicon content can exceed the reticle size of a single SoC. SIP includes traditional package substrates but also may includ... » read more

Launching The Full Potential Of 3D IC With Front-End Architectural Planning
By Siemens EDA - 19 Aug, 2025 - Comments: 0

3D IC and chiplet-based design have the potential to accelerate the pace of semiconductor industry innovation. 3D IC design teams pack more functionality closer together and achieve higher levels of systems integration and performance in a smaller footprint faster than what’s possible with traditional SoC implementation. To achieve the full potential of 3D IC, teams need cost-effective fro... » read more

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