Digital Engineering Transforms Chips For The Future


The semiconductor industry stands at a critical turning point. With global semiconductor sales exceeding $600 billion last year, the need for the industry to scale has never been more apparent. As AI applications drive unprecedented requirements for processing capabilities, chip designers are turning to advanced simulation technologies to enable the digital engineering workflows that will sup... » read more

Using Picosecond Ultrasonic Technology For AI Packages: Part 2


Heterogeneous integration is a key enabler of today’s AI innovations. By bringing together multiple chips with different functionalities, a.k.a., chiplets, AI devices have been able to achieve tremendous performance gains. However, the heterogeneous integration of advanced packages has its own set of process control obstacles that must be addressed, including new interconnect challenges invol... » read more

3D-IC Stress Analysis


The semiconductor industry is undergoing a transformation as 3D integrated circuits (ICs) and heterogeneous packaging become mainstream. With these advances comes the promise of higher functional density, a smaller footprint and enhanced system performance. However, these same innovations introduce new mechanical stressors within complex assemblies, posing novel reliability risks across the dev... » read more

3D Packaging vs 3D Integration eBook


In this eBook, you will: •    Explore the background and trends of multi-die packages •    Learn about the distinct approaches of 3D packaging and 3D integration •    Examine the challenges within heterogeneous integration Read more here. » read more

Industry Leaders Provide Insights And Guidance On Multi-Die Designs


Multi-die designs seamlessly integrate multiple heterogeneous or homogeneous dies in a single package to significantly enhance chip performance and efficiency — making them indispensable for high-performance computing (HPC), artificial intelligence (AI), data analytics, advanced graphics processing, and other demanding applications. While representing a groundbreaking leap forward, multi-d... » read more

Front-End Technologies Are The New Back-End Tools: Using Picosecond Ultrasonics Technology For AI Packages, Part 1


If you are a part of the semiconductor industry or simply someone interested in the field, you have likely heard what has become a common refrain: the back-end of the process is becoming more like the front-end of the process. In other words, the technologies that were once exclusively deployed in the first part of the process are being used to meet the increasingly stringent requirements of ad... » read more

Addressing Stress In Heterogeneous 3D-IC Designs


The benefits of 3D IC architectures are well-documented – smaller footprints, lower power, and increased performance. However, the move to heterogeneous 3D designs also introduces a host of new challenges that must be carefully navigated. As chip designers integrate multiple dies and technologies into a single 3D package, the interactions between the chip and package become increasingly co... » read more

Advanced Packaging Depends On Materials And Co-Design


Multi-die assemblies offer significant opportunities to boost performance and reduce power, but these complex packages also introduce a number of new challenges, including die-to-RDL misalignment, evolving warpage profiles, and CTE mismatch. Heterogeneous integration — an umbrella term that covers many different applications and packaging requirements — holds the potential to combine com... » read more

Floorplanning Method For Reducing Thermally-Induced Structural Stress In Chiplet Packages (Penn State, Intel, ASU et al.)


A new technical paper titled "STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration" was published by researchers at Pennsylvania State University, Intel, Arizona State University and University of Notre Dame. Abstract "Chiplet-based architectures and advanced packaging has emerged as transformative approaches in semiconductor design. While conventional ph... » read more

Chip Complexity Drives Innovation In Automated Test Equipment


Innovations in semiconductor technology—such as advancements in AI high-performance computing (HPC), Angstrom-scale silicon process nodes, silicon photonics, and automotive xEV wideband gap power transistor applications—require automated test equipment (ATE) to evolve at an unprecedented rate. As chip complexity grows, the challenges in design, manufacturing, and test multiply. It is a comp... » read more

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