tag: heterogeneous integration

Chiplet Hardware Security Module To Mitigate Security Vulnerabilities In SiP Systems (Univ. of Florida)
By Technical Paper Link - 09 Apr, 2024 - Comments: 0

A new technical paper titled "Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration" was published by researchers at University of Florida (Gainesville). Abstract: "The semiconductor industry has adopted heterogeneous integration (HI), incorporating modular intellectual property (IP) blocks (chiplets) into a unified syst... » read more

Interconnects Essential To Heterogeneous Integration
By Karen Heyman - 28 Mar, 2024 - Comments: 0

Designing and manufacturing interconnects is becoming more complex, and more critical to device reliability, as the chip industry shifts from monolithic planar dies to collections of chips and chiplets in a package. What was once as simple as laying down a copper trace has evolved into tens of thousands of microbumps, hybrid bonds, through-silicon vias (TSVs), and even junctions for optical ... » read more

Security Is Critical For Commercial Chiplets
By Ann Mutschler - 13 Mar, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the security issues and requirements in commercial chiplet ecosystem, with Frank Schirrmeister, vice president solutions and business development at Arteris; Mayank Bhatnagar, product marketing director in the Silicon Solutions Group at Cadence; Paul Karazuba, vice president of marketing at Expedera; Stephen Slater, EDA prod... » read more

Chiplet IP Standards Are Just The Beginning
By Ann Mutschler - 06 Mar, 2024 - Comments: 2

Experts at the Table: Semiconductor Engineering sat down to talk about chiplet standards, interoperability, and the need for highly customized AI chiplets, with Frank Schirrmeister, vice president solutions and business development at Arteris; Mayank Bhatnagar, product marketing director in the Silicon Solutions Group at Cadence; Paul Karazuba, vice president of marketing at Expedera; Stephen S... » read more

Commercial Chiplet Ecosystem May Be A Decade Away
By Ann Mutschler - 29 Feb, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the challenges of establishing a commercial chiplet ecosystem with Frank Schirrmeister, vice president solutions and business development at Arteris; Mayank Bhatnagar, product marketing director in the Silicon Solutions Group at Cadence; Paul Karazuba, vice president of marketing at Expedera; Stephen Slater, EDA product mana... » read more

Integration Challenges For RISC-V Designs
By Ed Sperling - 27 Feb, 2024 - Comments: 0

One of the big draws of RISC-V is that it allows design teams to create unique chips or chiplets and to make modifications to the instruction-set architecture. That extra degree of freedom also creates some issues when it comes to integrating those designs into packages or systems because they may require non-standard connectivity approaches. Frank Schirrmeister, vice president of marketing at ... » read more

Thinking Big: From Chips To Systems
By Ed Sperling - 27 Feb, 2024 - Comments: 0

Semiconductor Engineering sat down with Aart de Geus, executive chair and founder of Synopsys, to talk about the shift from chips to systems, next-generation transistors, and what's required to build multi-die devices in the context of rapid change and other systems. SE: What are the biggest changes you're seeing in the chip industry these days, and why now? de Geus: It's not just the siz... » read more

New Issues In Power Semiconductors
By Ed Sperling - 26 Feb, 2024 - Comments: 0

The number of challenges is growing in power semiconductors, just as it is in traditional chips. Thermal dissipation and gradients, new design rules, and layout issues need to be considered, especially in the context of higher voltage and increased performance demands. Roland Jancke, design methodology head in Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about issues in int... » read more

The Seven Pillars Of IC Package Physical Design
By Keith Felton - 15 Feb, 2024 - Comments: 0

Today’s heterogeneously integrated semiconductor packages represent a breakthrough technology that enables dramatic increases in bandwidth and performance with reduced power and cost compared to what can be currently achieved in traditional monolithic SoC designs. Figure 1. A heterogeneously integrated device with 47 chiplets. (Image Source: Intel) The evolving landscape of packagin... » read more

Heterogeneous Integration And Electronics Packaging Manufacturing Roadmap (SEMI & UCLA)
By Technical Paper Link - 09 Feb, 2024 - Comments: 0

A report titled “Manufacturing Roadmap for Heterogeneous Integration and Electronics Packaging (MRHIEP)” was published by researchers at SEMI and the University of California Los Angeles (UCLA)'s Center for Heterogeneous Integration and Performance Scaling (CHIPS), and funded by the National Institute of Standards and Technology (NIST). MRHIEP Goals: "The goal of MRHIEP is to develop an o... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy