Integrated, Turnkey Droop Response System: Heterogeneous IP Use Case


Whether you serve the ADAS, PC, or networking market, chances are that your SoC is heterogeneous; containing general processors and application-specific accelerators. Your solution might have a systolic array for convolutions, a cluster of CPUs for application code, or a look-aside crypto engine for packet security. While application-specific accelerators significantly improve performance and p... » read more

Tech Talk: Timing Closure


Arteris' George Janac talks about timing closure issues in advanced chips and why this has reared its head again for the first time in a decade.   Related Stories Timing Closure Issues Resurface Adding more features and more power states is making it harder to design chips at 10nm and 7nm. » read more

Easing Heterogeneous Cache Coherent SoC Design Using Arteris’ Ncore Interconnect IP


Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and network-on-a-chip (NoC) technology are the first step, giving architects IP to efficiently connect compute processing elements as different as CPUs, GPUs, and DSPs. Hardware IP to enable coherent communication bet... » read more