tag: heterogeneous SoCs

On-Chip Communication For Programmable Accelerators In Heterogeneous SoCs (Columbia, IBM)
By Technical Paper Link - 10 Jul, 2024 - Comments: 0

A technical paper titled “Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures” was published by researchers at Columbia University and IBM Thomas J. Watson Research Center. Abstract: "We present several enhancements to the open-source ESP platform to support flexible and efficient on-chip communication for programmable accelerators in het... » read more

Integrated, Turnkey Droop Response System: Heterogeneous IP Use Case
By Movellus - 29 May, 2024 - Comments: 0

Whether you serve the ADAS, PC, or networking market, chances are that your SoC is heterogeneous; containing general processors and application-specific accelerators. Your solution might have a systolic array for convolutions, a cluster of CPUs for application code, or a look-aside crypto engine for packet security. While application-specific accelerators significantly improve performance and p... » read more

Tech Talk: Timing Closure
By Ed Sperling - 29 Dec, 2016 - Comments: 0

Arteris' George Janac talks about timing closure issues in advanced chips and why this has reared its head again for the first time in a decade.   Related Stories Timing Closure Issues Resurface Adding more features and more power states is making it harder to design chips at 10nm and 7nm. » read more

Easing Heterogeneous Cache Coherent SoC Design Using Arteris’ Ncore Interconnect IP
By Arteris - 24 Aug, 2016 - Comments: 0

Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and network-on-a-chip (NoC) technology are the first step, giving architects IP to efficiently connect compute processing elements as different as CPUs, GPUs, and DSPs. Hardware IP to enable coherent communication bet... » read more

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