tag: high-level synthesis

Future-proofing AI Models
By Ann Mutschler - 21 May, 2025 - Comments: 0

Experts At The Table: Making sure AI accelerators can be updated for future requirements is becoming essential due to the rapid introduction of new models. Semiconductor Engineering sat down to discuss the challenges of future-proofing these designs with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vic... » read more

AI Accelerators Moving Out From Data Centers
By Ann Mutschler - 15 May, 2025 - Comments: 0

Experts At The Table: The explosion in AI data is driving chipmakers to look beyond a single planar SoC. Semiconductor Engineering sat down to discuss the need for more computing and the expanding role of chiplets with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vice president of marketing at Expedera; ... » read more

LLMs In The High-Level Synthesis Design Flow
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Are LLMs Any Good for High-Level Synthesis?" was published by researchers at University of Arizona. Abstract "The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS proces... » read more

Fantastical Creatures
By Russell Klein - 12 Aug, 2024 - Comments: 2

In my day job I work in the High-Level Synthesis group at Siemens EDA, specifically focusing on algorithm acceleration. But on the weekends, sometimes, I take on the role of amateur cryptozoologist. As many of you know, the main Siemens EDA campus sits in the shadow of Mt. Hood and the Cascade Mountain range. This is prime habitat for Sasquatch, also known as “Bigfoot”. This weekend, ar... » read more

High-Level Synthesis Propels Next-Gen AI Accelerators
By Russell Klein - 20 May, 2024 - Comments: 0

Everything around you is getting smarter. Artificial intelligence is not just a data center application but will be deployed in all kinds of embedded systems that we interact with daily. We expect to talk to and gesture at them. We expect them to recognize and understand us. And we expect them to operate with just a little bit of common sense. This intelligence is making these systems not just ... » read more

Will Domain-Specific ICs Become Ubiquitous?
By Brian Bailey - 16 May, 2024 - Comments: 0

Questions are surfacing for all types of design, ranging from small microcontrollers to leading-edge chips, over whether domain-specific design will become ubiquitous, or whether it will fall into the historic pattern of customization first, followed by lower-cost, general-purpose components. Custom hardware always has been a double-edged sword. It can provide a competitive edge for chipmake... » read more

High-Level Synthesis Enables The Next Generation Of Edge AI Accelerators
By Siemens EDA - 15 May, 2024 - Comments: 0

AI is becoming pervasive. But the ever increasing complexity is a challenge for IoT systems. Achieving the highest levels of performance and efficiency in edge AI means going beyond software and off the shelf hardware. Bespoke hardware accelerators in FPGA or ASICs can deliver much higher performance while consuming less energy. Building these accelerators with High-Level Synthesis slashes desi... » read more

Communication Is Key To Finding And Fixing Bugs In ICs
By Ann Mutschler and Adam Kovac - 08 May, 2024 - Comments: 0

Experts at the Table: Finding and eliminating bugs at the source can be painstaking work, but it also can prevent even greater problems from developing later on. To examine the best ways to tackle this problem, Semiconductor Engineering sat down with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software product manager ... » read more

Engineers Or Their Tools: Which Is Responsible For Finding Bugs?
By Ann Mutschler and Adam Kovac - 28 Mar, 2024 - Comments: 0

Experts at the table: Finding and eliminating bugs at the source can be painstaking work, but it can prevent bigger problems later in the design flow, when they are more difficult and expensive to fix.  Semiconductor Engineering sat down to discuss these issues with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software... » read more

How The Productivity Advantages Of High-Level Synthesis Can Improve IP Design, Verification, And Reuse
By Cadence - 06 Dec, 2023 - Comments: 0

Engineering teams are under more pressure than ever before—systems on chip (SoCs) are growing more complex and design schedules are increasingly tighter. With its productivity advantages, high-level synthesis (HLS) has long been touted as part of the solution, but its sweet spot has traditionally been limited to datapath-centric blocks. Moreover, design productivity is only one part of ... » read more

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