tag: high-level synthesis

Using HLS To Improve Algorithms
By Zubair Wadood - 24 Oct, 2019 - Comments: 0

Can an HLS optimization tool outperform expert-level hand-optimizations? A recently published white paper examines how SLX FPGA is used to optimize a secure hash algorithm. T the results are compared to a competition-winning hand-optimized HLS implementation of the same algorithm. This approach provides a nearly 400x speed-up over the unoptimized implementation and even outperforms the hand ... » read more

Focus Shifts To Wasted Power
By Brian Bailey - 10 Oct, 2019 - Comments: 0

Mobile phones made the industry aware of power, but now the focus is shifting to the total energy needed to perform a task. Activity that is unnecessary to perform the intended task is wasted power, and reducing it requires some new methodologies and structural changes within development teams. There is a broadening awareness about power. "The companies doing SoCs for mobile lead the charge ... » read more

High-Level Design And High-Level Verification
By Dominik Strasser - 26 Sep, 2019 - Comments: 0

Not so long ago, some EDA vendors were painting a very attractive picture of chip design in the then-near future. The idea was that an architectural team would write a single description of the complete system in some high-level language, usually C/C++/SystemC, and that a new class of EDA tool would automatically partition the design into hardware and software, choosing the functionality of eac... » read more

Machine Learning For Autonomous Drive
By Anoop Saha - 05 Sep, 2019 - Comments: 0

Advances in Artificial Intelligence (AI) and Machine Learning (ML) is arguably the biggest technical innovation of the last decade. Although the algorithms for AI have been in existence for many years, the recent explosion of both data as well as faster compute made it possible to apply those algorithms to solve many real life use cases. One of the most prominent of these use cases is fully aut... » read more

Synthesizing Hardware From Software
By Brian Bailey - 22 Aug, 2019 - Comments: 1

The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible. While high-level synthesis (HLS) did come out of this work and has proven to be... » read more

Debug Tools Are Improving
By Brian Bailey - 12 Aug, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss debugging complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions. Part one can be found here. Part two... » read more

High-Level Synthesis For Autonomous Drive
By Mentor, a Siemens Business - 31 Jul, 2019 - Comments: 0

The sensors in autonomous vehicles continuously generate a high volume of data in real time about the environment surrounding the car. The vehicles need new hardware architectures to be able to process this data quickly and make decisions that enable self driving. Catapult, the industry’s leading High-Level Synthesis (HLS) platform, provides a new paradigm of designing silicon at a higher lev... » read more

Hardware-Software Co-Design Reappears
By Brian Bailey - 25 Jul, 2019 - Comments: 1

The core concepts in hardware-software co-design are getting another look, nearly two decades after this approach was first introduced and failed to catch on. What's different this time around is the growing complexity and an emphasis on architectural improvements, as well as device scaling, particularly for AI/ML applications. Software is a critical component, and the more tightly integrate... » read more

Optimize MATLAB C/C++ Code For HLS
By Zubair Wadood - 25 Jul, 2019 - Comments: 0

A common use case for high-level synthesis (HLS) is taking 3rd party generated or legacy C/C++ algorithms and converting the algorithm to a hardware implementation using an HLS compiler. This can present many challenges to the developer since there is little insight or understanding of the underlying code. In a recently published white paper, we examine how SLX FPGA is used to take a MATLAB... » read more

Konica Minolta Proves C++ Level Signoff Possibilities Using Catapult HLS Platform
By Mentor, a Siemens Business - 24 Jul, 2019 - Comments: 0

A team’s ultimate goal is to move verification up to the C++ level in order to minimize the time spent in RTL verification and to achieve C++ signoff. A team at Konica Minolta® has been using the Catapult HLS Platform for many years to dramatically improve their productivity by coding at the C++ level and using the platform to generate RTL. They recently evaluated the high-level verification... » read more

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