tag: high-level synthesis

Hardware-Software Co-Design Reappears
By Brian Bailey - 25 Jul, 2019 - Comments: 1

The core concepts in hardware-software co-design are getting another look, nearly two decades after this approach was first introduced and failed to catch on. What's different this time around is the growing complexity and an emphasis on architectural improvements, as well as device scaling, particularly for AI/ML applications. Software is a critical component, and the more tightly integrate... » read more

Optimize MATLAB C/C++ Code For HLS
By Zubair Wadood - 25 Jul, 2019 - Comments: 0

A common use case for high-level synthesis (HLS) is taking 3rd party generated or legacy C/C++ algorithms and converting the algorithm to a hardware implementation using an HLS compiler. This can present many challenges to the developer since there is little insight or understanding of the underlying code. In a recently published white paper, we examine how SLX FPGA is used to take a MATLAB... » read more

Konica Minolta Proves C++ Level Signoff Possibilities Using Catapult HLS Platform
By Mentor, a Siemens Business - 24 Jul, 2019 - Comments: 0

A team’s ultimate goal is to move verification up to the C++ level in order to minimize the time spent in RTL verification and to achieve C++ signoff. A team at Konica Minolta® has been using the Catapult HLS Platform for many years to dramatically improve their productivity by coding at the C++ level and using the platform to generate RTL. They recently evaluated the high-level verification... » read more

Providing An AI Accelerator Ecosystem
By David Burnette - 27 Jun, 2019 - Comments: 0

A key design area for AI systems is the creation of Machine Learning (ML) algorithms that can be accelerated in hardware to meet power and performance goals. Teams designing these algorithms find out quickly that a traditional RTL design flow will no longer work if they want to meet their delivery schedules. The algorithms are often subject to frequent changes, the performance requirements may ... » read more

Formally Ensuring Equivalence Between C++ And RTL Designs
By Mentor, a Siemens Business - 26 Jun, 2019 - Comments: 0

Moving untimed C++ design descriptions through a High-Level Synthesis (HLS) flow, designers wonder if the generated, timed RTL is functionally equivalent to the original, high-level description. When they make refinements or optimize RTL for power, they naturally are concerned that these changes no longer meet their original specifications. They could create testbenches and run verification at ... » read more

CEO Outlook: Rising Costs, Chiplets, And A Trade War
By Ed Sperling - 26 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

Machine Learning Drives High-Level Synthesis Boom
By Kevin Fogarty - 06 Jun, 2019 - Comments: 0

High-level synthesis (HLS) is experiencing a new wave of popularity, driven by its ability to handle machine-learning matrices and iterative design efforts. The obvious advantage of HLS is the boost in productivity designers get from working in C, C++ and other high-level languages rather than RTL. The ability to design a layout that should work, and then easily modify it to test other confi... » read more

Building An Efficient Inferencing Engine In A Car
By Ed Sperling - 05 Jun, 2019 - Comments: 0

David Fritz, who heads corporate strategic alliances at Mentor, a Siemens Business, talks about how to speed up inferencing by taking the input from sensors and quickly classifying the output, but also doing that with low power. » read more

How To Integrate An Embedded FPGA
By Brian Bailey - 30 May, 2019 - Comments: 1

Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric ... » read more

Challenges In Using HLS For FPGA Design
By Loren Hobbs - 29 Apr, 2019 - Comments: 0

High-level synthesis (HLS) tools, which transform C/C++ source code to Verilog/VHDL, have been commercially available for over 15 years. HLS tools from FPGA vendors and EDA companies promise improved productivity through a higher-level of abstraction, faster verification and quicker design iterations. For example, simulating your design in C/C++ can be 10 to 100x faster than simulating in RTL (... » read more

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