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Why Mask Blanks Are Critical


Geoff Akiki, president of Hoya LSI at the Hoya Group, sat down with Semiconductor Engineering to talk about optical and extreme ultraviolet (EUV) lithography as well as mask blanks. What follows are excerpts of that discussion. SE: Mask blanks are components that serve as the base or the substrate for a photomask. Why are they critical? Akiki: If you look at Hoya, we've been positioned as... » read more

Gearing Up For High-NA EUV


The semiconductor industry is moving full speed ahead to develop high-NA EUV, but bringing up this next generation lithography system and the associated infrastructure remains a monumental and expensive task. ASML has been developing its high-numerical aperture (high-NA) EUV lithography line for some time. Basically, high-NA EUV scanners are the follow-on to today’s EUV lithography systems... » read more

Inside Intel’s Ambitious Roadmap


Ann Kelleher, senior vice president and general manager of Technology Development at Intel, sat down with Semiconductor Engineering to talk about the company’s new logic roadmap, as well as lithography, packaging, and process technology. What follows are excerpts of that discussion. SE: Intel recently disclosed its new logic roadmap. Beyond Intel 3, the company is working on Intel 20A. Wit... » read more

What’s Next In Fab Tool Technologies?


Experts at the Table: Semiconductor Engineering sat down to discuss extreme ultraviolet (EUV) lithography and other next-generation fab technologies with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fuj... » read more

EUV Pellicles Finally Ready


After a period of delays, EUV pellicles are emerging and becoming a requirement in high-volume production of critical chips. At the same time, the pellicle landscape for extreme ultraviolet (EUV) lithography is changing. ASML, the sole supplier of EUV pellicles, is transferring the assembly and distribution of these products to Mitsui. Others are also developing pellicles for EUV, a next-gen... » read more

Manufacturing Bits: March 8


Two-beam EUV lithography At the recent SPIE Advanced Lithography conference, Nikon gave a presentation on a two-beam extreme ultraviolet (EUV) lithography technology. Still in the conceptual phase, Nikon’s so-called EUV Projection Optical Wafer Exposure Ruling Machine, or EUV Power Machine, is designed for the 1nm node or so. The proposed system has a minimum resolution of 10nm for lines ... » read more

AI And High-NA EUV At 3/2/1nm


Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

EUV Challenges And Unknowns At 3nm and Below


The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up. In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV pro... » read more

Challenges Linger For EUV


Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

New Architectures, Much Faster Chips


The chip industry is making progress in multiple physical dimensions and with multiple architectural approaches, setting the stage for huge performance increases based on more modular and heterogeneous designs, new advanced packaging options, and continued scaling of digital logic for at least a couple more process nodes. A number of these changes have been discussed in recent conferences. I... » read more

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