tag: high-performance computing

Conquer Placement And Clock Tree Challenges In HPC Designs
By Janet Attar - 11 May, 2023 - Comments: 0

High-performance computing (HPC) applications require IC designs with maximum performance. However, as process technology advances, achieving high performance has become increasingly challenging. Designers need digital implementation tools and methodologies that can solve the thorny issues in HPC designs, including placement and clock tree challenges. Placement and clock tree synthesis are c... » read more

Placement And CTS Techniques For High-Performance Computing Designs
By Siemens EDA - 10 May, 2023 - Comments: 0

This paper discusses the challenges of designing high-performance computing (HPC) integrated circuits (ICs) to achieve maximum performance. The design process for HPC ICs has become more complex with each new process technology, requiring new architectures and transistors. We highlight how the Siemens Aprisa digital implementation solution can solve placement and clock tree challenges in HPC de... » read more

RISC-V Vectorization And Potential for HPC
By Technical Paper Link - 26 Apr, 2023 - Comments: 0

A new technical paper titled "Test-driving RISC-V Vector hardware for HPC" was published by researchers at University of Edinburgh. Abstract: "Whilst the RISC-V Vector extension (RVV) has been ratified, at the time of writing both hardware implementations and open source software support are still limited for vectorisation on RISC-V. This is important because vectorisation is crucial to obt... » read more

A RISC-V On-Chip Parallel Power Controller for HPC (ETH Zurich, U. of Bologna)
By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A new technical paper titled "ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation" was published (preprint) by researchers at ETH Zurich and University of Bologna. Abstract (partial) "High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex an... » read more

Is RISC-V Ready For Supercomputing?
By Brian Bailey - 09 Feb, 2023 - Comments: 0

RISC-V processors, which until several years ago were considered auxiliary processors for specific functions, appear to be garnering support for an entirely different type of role — high-performance computing. This is still at the discussion stage. Questions remain about the software ecosystem, or whether the chips, boards, and systems are reliable enough. And there are both business and t... » read more

How To Raise Reliability, Availability, And Serviceability Levels For HPC SoCs
By Charlie Matar - 09 Feb, 2023 - Comments: 0

By Charlie Matar, Rita Horner, and Pawini Mahajan While once the domain of large data centers and supercomputers, high-performance computing (HPC) has become rather ubiquitous and, in some cases, essential in our everyday lives. Because of this, reliability, availability, and serviceability, or RAS, is a concept that more HPC SoC designers should familiarize themselves with. RAS may sound... » read more

Mitigating Silent Data Corruptions in High Performance Computing
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A new technical paper titled "Mitigating silent data corruptions in HPC applications across multiple program inputs" was published by researchers at University of Iowa, Baidu Security, and Argonne National Lab. The paper was a Best Paper finalist at SC22. The researchers "propose MinpSID, an automated SID framework that automatically identifies and re-prioritizes incubative instructions in a... » read more

The Path To Known Good Interconnects
By Laura Peters - 19 Jan, 2023 - Comments: 1

Chiplets and heterogenous integration (HI) provide a compelling way to continue delivering improvements in performance, power, area, and cost (PPAC) as Moore’s Law slows, but choosing the best way to connect these devices so they behave in consistent and predictable ways is becoming a challenge as the number of options continues to grow. More possibilities also bring more potential interac... » read more

RISC-V decoupled Vector Processing Unit (VPU) For HPC
By Technical Paper Link - 20 Dec, 2022 - Comments: 0

A technical paper titled "Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications" was published by researchers at Barcelona Supercomputing Center, Spain. "The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of ... » read more

Chip Sandwich: Electronics Chip & Photonics Chip Co-Optimized To Work Together (CalTech/Univ. of Southampton)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators" was published by researchers at CalTech and University of Southampton. "The resulting optimized interface between the two chips allows them to transmit 100 gigabits of data per second while producing just 2.4 pico-Joules per transmitted bit. This improves th... » read more

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