tag: HLS

Optimizing Hardware Faster
By Ed Sperling - 26 Nov, 2019 - Comments: 0

Maximillian Odendahl, CEO of Silexica, sat down with Semiconductor Engineering to talk about high-level synthesis and the changing role of this technology. What follows are excerpts of that conversation. SE: What is the direction that high-level synthesis is heading in? Odendahl: The direction hasn’t changed, but in the past HLS was not usable by the software guys. The main push right n... » read more

Accelerating Financial Applications With SLX FPGA
By Silexica - 25 Nov, 2019 - Comments: 0

This white paper demonstrates how engineers creating FPGA-based hardware accelerators for financial market models can take advantage of SLX FPGA. SLX FPGA can be used to accelerate optimization efforts for financial market models targeting option pricing. In this paper, two implementations of computation intensive models for pricing options are discussed, namely the Black-Scholes and Heston pri... » read more

Rapid Evolution For Verification Plans
By Brian Bailey - 28 Oct, 2019 - Comments: 0

Verification plans are rapidly evolving from mechanisms to track verification progress into multi-faceted coordination vehicles for several teams with disparate goals, using complex resource management spread across multiple abstractions and tools. New system demands from industries such as automotive are forcing tighter integration of those plans with requirements management and product lif... » read more

Does System Design Still Need Abstraction?
By Frank Schirrmeister - 24 Oct, 2019 - Comments: 0

About 15 years ago, the assumption in the EDA industry was that system design would be inevitable. The transition from gate-level design to a new entry point at the register transfer level (RTL) seemed complete with logic synthesis becoming well-adopted. The next step seemed to be so obvious at the time: High-level synthesis (HLS) and transaction-based development beyond RTL—also taking into ... » read more

Using HLS To Improve Algorithms
By Zubair Wadood - 24 Oct, 2019 - Comments: 0

Can an HLS optimization tool outperform expert-level hand-optimizations? A recently published white paper examines how SLX FPGA is used to optimize a secure hash algorithm. T the results are compared to a competition-winning hand-optimized HLS implementation of the same algorithm. This approach provides a nearly 400x speed-up over the unoptimized implementation and even outperforms the hand ... » read more

Using SLX FPGA For Performance Optimization Of SHA-3 For HLS
By Silexica - 23 Oct, 2019 - Comments: 0

Author: Zubair Wadood SLX FPGA facilitates converting your C/C++ project into an FPGA bitstream easier and with higher performance. Leveraging standard HLS (High Level Synthesis) tools from FPGA vendors, SLX FPGA tackles the challenges associated with the HLS design flow. In this paper, the results of an SLX FPGA-optimized implementation of a Secure Hash Algorithm (SHA-3; also known as Kecca... » read more

High-Level Design And High-Level Verification
By Dominik Strasser - 26 Sep, 2019 - Comments: 0

Not so long ago, some EDA vendors were painting a very attractive picture of chip design in the then-near future. The idea was that an architectural team would write a single description of the complete system in some high-level language, usually C/C++/SystemC, and that a new class of EDA tool would automatically partition the design into hardware and software, choosing the functionality of eac... » read more

Machine Learning For Autonomous Drive
By Anoop Saha - 05 Sep, 2019 - Comments: 0

Advances in Artificial Intelligence (AI) and Machine Learning (ML) is arguably the biggest technical innovation of the last decade. Although the algorithms for AI have been in existence for many years, the recent explosion of both data as well as faster compute made it possible to apply those algorithms to solve many real life use cases. One of the most prominent of these use cases is fully aut... » read more

Synthesizing Hardware From Software
By Brian Bailey - 22 Aug, 2019 - Comments: 1

The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible. While high-level synthesis (HLS) did come out of this work and has proven to be... » read more

Facilitating High Level Synthesis from MATLAB generated C C++
By Silexica - 21 Aug, 2019 - Comments: 0

MATLAB is the go-to toolbox for high level algorithm design in many application domains, ranging from signal processing to control systems and data analysis. MATLAB Coder generates executable C/C++ code from MATLAB implementations. However, the performance requirements of these applications often mandate a hardware implementation. SLX FPGA helps transform the auto-generated C/C++ code into a sy... » read more

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