Improving Semiconductor Yield Using Large Area Analysis

By Jacky Huang - 19 Dec, 2023 - Comments: 0

Design rule checking (DRC) is a technique used during chip design to ensure that a device can successfully be manufactured at high yield. Design rules are established based on the limits and variability of equipment and process technologies in use. DRC checking ensures that a design meets manufacturing requirements and will not result in a chip failure or DRC “violation.” Common DRC rules i... » read more

Fast LFD Flows With Pattern Matching And Machine Learning Can Deliver Higher-Yielding Designs Faster

By Wael elManhawy - 22 Aug, 2019 - Comments: 0

By Wael ElManhawy and Joe Kwan A lithographic (litho) hotspot is a defect on a wafer that is created during manufacturing by a combination of systematic process variation and resolution enhancement technology (RET) limitations. Litho hotspots typically represent severe yield detractors, so detecting and eliminating potential litho hotspots prior to manufacturing is crucial to achieving a com... » read more

Achieve High Hotspot Detection Accuracy by Pattern Scoring

By UMC - 14 Dec, 2018 - Comments: 0

In this paper, we combined the hotspot pattern library and the rule-based scoring system into a modularized hotspot-checking rule deck running on an automatic flow. Several DFM (design for manufacture) properties criteria will be defined to build a “score board” for hotspot candidates. When hotspots in the input design are highlighted, the scoring system can identify whether a hotspot is a ... » read more

Process Window Discovery And Control

By Andrew Cross - 18 Dec, 2017 - Comments: 0

With the continued need for shrinking pattern dimensions, semiconductor manufacturers continue to implement more complex patterning techniques, such as advanced multi-patterning, for the 10nm design node and beyond. They also are investing significant development effort in readying EUV lithography for production at the 7/5nm design nodes. Additionally, semiconductor manufacturers’ use of desi... » read more

Creating An Accurate FEOL CMP Model

By Jeff Wilson - 20 Oct, 2016 - Comments: 0

By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid For decades, semiconductor manufacturers have used chemical-mechanical polishing (CMP) as the primary technique for the smoothing and leveling (planarization) of dielectrics and metal layers. CMP modeling allows design and manufacturing teams to find and fix potential planarization issues before the actual CMP process is applied to a ... » read more

Design Process Technology Co-Optimization For Manufacturability

By Dalong Zhao - 22 Sep, 2016 - Comments: 0

Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node. Design for manufacturability (DFM) and design process technology... » read more

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eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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tag: hotspots

Improving Semiconductor Yield Using Large Area Analysis

Fast LFD Flows With Pattern Matching And Machine Learning Can Deliver Higher-Yielding Designs Faster

Achieve High Hotspot Detection Accuracy by Pattern Scoring

Process Window Discovery And Control

Creating An Accurate FEOL CMP Model

Design Process Technology Co-Optimization For Manufacturability

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