tag: HPC

Lines Blurring Between Supercomputing And HPC
By Ann Mutschler - 27 Feb, 2025 - Comments: 1

Supercomputers and high-performance computers are becoming increasingly difficult to differentiate due to the proliferation of AI, which is driving huge performance increases in commercial and scientific applications and raising similar challenges for both. While the goals of supercomputing and high-performance computing (HPC) have always been similar — blazing fast processing — the mark... » read more

Bold Prediction: 50% Of New HPC Chip Designs Will Be Multi-Die In 2025
By Shekhar Kapoor - 27 Feb, 2025 - Comments: 0

Monolithic chips have been the workhorses behind decades of technological advancement. But just as the industrial revolution saw workhorses replaced with more efficient and powerful machinery, the semiconductor industry is on the cusp of a similar revolution. Multi-die and chiplet-based designs — which integrate multiple specialized dies in a single package or stack integrated circuits ver... » read more

Signal Integrity Plays Increasingly Critical Role In Chiplet Design
By Ann Mutschler - 13 Feb, 2025 - Comments: 1

Maintaining the quality and reliability of electrical signals as they travel through interconnects is proving to be much more challenging with chiplets and advanced packaging than in monolithic SoCs and PCBs. Signal integrity is a fundamental requirement for all chips and systems, but it becomes more difficult with chiplets due to reflections, loss, crosstalk, process variation, and various ... » read more

Uncore Frequency Scaling For Energy Optimization In Heterogeneous Systems (UIC, Argonne)
By Technical Paper Link - 12 Feb, 2025 - Comments: 0

A new technical paper titled "Exploring Uncore Frequency Scaling for Heterogeneous Computing" was published by researchers at University of Illinois Chicago and Argonne National Laboratory. Abstract "High-performance computing (HPC) systems are essential for scientific discovery and engineering innovation. However, their growing power demands pose significant challenges, particularly as sys... » read more

Chiplets: Where Are We Today?
By Barry Pangrle - 05 Feb, 2025 - Comments: 1

The 3rd annual Chiplet Summit was held in Santa Clara from January 21st to 23rd at the Convention Center. The conference continues to grow from its 1st year when it was held at the San Jose Doubletree Hotel (almost exactly 2 years ago). During his Chairman’s Welcome presentation, Chuck Sobey mentioned that there were 41 exhibitors at this year’s conference. Chuck was also the moderator f... » read more

How Ultra Ethernet And UALink Enable High-Performance, Scalable AI Networks
By Ron Lowman - 16 Jan, 2025 - Comments: 0

By Ron Lowman and Jon Ames AI workloads are significantly driving innovation in the interface IP market. The exponential increase in AI model parameters, doubling approximately every 4-6 months, stands in stark contrast to the slower pace of hardware advancements dictated by Moore's Law, which follows an 18-month cycle. This discrepancy demands hardware innovations to support AI workloads, c... » read more

CXL’s Potential to Elevate The Capabilities of HPC and AI Applications (Micron, Intel)
By Technical Paper Link - 20 Dec, 2024 - Comments: 0

A new technical paper titled "Optimizing System Memory Bandwidth with Micron CXL Memory Expansion Modules on Intel Xeon 6 Processors" was published by researchers at Micron and Intel. Abstract "High-Performance Computing (HPC) and Artificial Intelligence (AI) workloads typically demand substantial memory bandwidth and, to a degree, memory capacity. CXL memory expansion modules, also known... » read more

Integrating Ethernet, PCIe, And UCIe For Enhanced Bandwidth And Scalability For AI/HPC Chips
By Madhumita Sanyal - 12 Dec, 2024 - Comments: 0

By Madhumita Sanyal and Aparna Tarde Multi-die architectures are becoming a pivotal solution for boosting performance, scalability, and adaptability in contemporary data centers. By breaking down traditional monolithic designs into smaller, either heterogeneous or homogeneous dies (also known as chiplets), engineers can fine-tune each component for specific functions, resulting in notable im... » read more

Distributed Shared Memory That Enlarges Effective Memory Capacity Through Intelligent Tiered DRAM and Storage Management (IIT)
By Technical Paper Link - 13 Nov, 2024 - Comments: 0

A new technical paper titled "MegaMmap: Blurring the Boundary Between Memory and Storage for Data-Intensive Workloads" was published by researchers at Illinois Institute of Technology. "In this work, we propose MegaMmap: a software distributed shared memory (DSM) that enlarges effective memory capacity through intelligent tiered DRAM and storage management. MegaMmap provides workload-aware d... » read more

Understanding The Total Cost Of Ownership In HPC And AI Systems
By Wim Slagter - 12 Sep, 2024 - Comments: 0

Cost is often the deciding factor when it comes to purchasing decisions at an organization, particularly those dealing with high-tech investments. When organizations evaluate proposals for new procurements, the initial capital cost of the system often receives significant attention. A great deal of preparation and planning goes into the decision to make a large purchase. While this is a critica... » read more

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