tag: HPC

Chiplets: Where Are We Today?
By Barry Pangrle - 05 Feb, 2025 - Comments: 1

The 3rd annual Chiplet Summit was held in Santa Clara from January 21st to 23rd at the Convention Center. The conference continues to grow from its 1st year when it was held at the San Jose Doubletree Hotel (almost exactly 2 years ago). During his Chairman’s Welcome presentation, Chuck Sobey mentioned that there were 41 exhibitors at this year’s conference. Chuck was also the moderator f... » read more

How Ultra Ethernet And UALink Enable High-Performance, Scalable AI Networks
By Ron Lowman - 16 Jan, 2025 - Comments: 0

By Ron Lowman and Jon Ames AI workloads are significantly driving innovation in the interface IP market. The exponential increase in AI model parameters, doubling approximately every 4-6 months, stands in stark contrast to the slower pace of hardware advancements dictated by Moore's Law, which follows an 18-month cycle. This discrepancy demands hardware innovations to support AI workloads, c... » read more

CXL’s Potential to Elevate The Capabilities of HPC and AI Applications (Micron, Intel)
By Technical Paper Link - 20 Dec, 2024 - Comments: 0

A new technical paper titled "Optimizing System Memory Bandwidth with Micron CXL Memory Expansion Modules on Intel Xeon 6 Processors" was published by researchers at Micron and Intel. Abstract "High-Performance Computing (HPC) and Artificial Intelligence (AI) workloads typically demand substantial memory bandwidth and, to a degree, memory capacity. CXL memory expansion modules, also known... » read more

Integrating Ethernet, PCIe, And UCIe For Enhanced Bandwidth And Scalability For AI/HPC Chips
By Madhumita Sanyal - 12 Dec, 2024 - Comments: 0

By Madhumita Sanyal and Aparna Tarde Multi-die architectures are becoming a pivotal solution for boosting performance, scalability, and adaptability in contemporary data centers. By breaking down traditional monolithic designs into smaller, either heterogeneous or homogeneous dies (also known as chiplets), engineers can fine-tune each component for specific functions, resulting in notable im... » read more

Distributed Shared Memory That Enlarges Effective Memory Capacity Through Intelligent Tiered DRAM and Storage Management (IIT)
By Technical Paper Link - 13 Nov, 2024 - Comments: 0

A new technical paper titled "MegaMmap: Blurring the Boundary Between Memory and Storage for Data-Intensive Workloads" was published by researchers at Illinois Institute of Technology. "In this work, we propose MegaMmap: a software distributed shared memory (DSM) that enlarges effective memory capacity through intelligent tiered DRAM and storage management. MegaMmap provides workload-aware d... » read more

Understanding The Total Cost Of Ownership In HPC And AI Systems
By Wim Slagter - 12 Sep, 2024 - Comments: 0

Cost is often the deciding factor when it comes to purchasing decisions at an organization, particularly those dealing with high-tech investments. When organizations evaluate proposals for new procurements, the initial capital cost of the system often receives significant attention. A great deal of preparation and planning goes into the decision to make a large purchase. While this is a critica... » read more

Reimagine Enterprise Data Center Design and Operations
By Cadence - 11 Sep, 2024 - Comments: 0

The Power of Digital Twin Technology This eBook showcases how large enterprises across various industries, such as aerospace, healthcare, automotive and financial services, use digital twin software to overcome unique challenges, resulting in: 30-40% reduction in power consumption and increased efficiency Extended data center lifespan and resisted cloud migration pressures Impro... » read more

IC Power Optimization Required, But More Difficult To Achieve
By Adam Kovac - 18 Jul, 2024 - Comments: 0

Power optimization is playing an increasingly vital role in chip and chip and system designs, but it's also becoming much harder to achieve as transistor density and system complexity continue to grow. This is especially evident with advanced packages, chiplets, and high-performance chips, all of which are becoming more common in complex designs. Inside data centers, racks of servers are str... » read more

Delivering On Power During HPC Test
By Anne Meixner - 09 Jul, 2024 - Comments: 0

The industry’s insatiable need for power in high-performance computing (HPC) is creating problems for test cells, which need to deliver very high currents at very consistent voltage levels through the power delivery network (PDN). In response, ATE, wafer probe, and contactor vendors are introducing some innovative approaches and test procedures that can ensure robust power delivery to ATE pro... » read more

Characterizing and Evaluating A Quantum Processor Unit In A HPC Center
By Technical Paper Link - 10 Jun, 2024 - Comments: 0

A new technical paper titled "Calibration and Performance Evaluation of a Superconducting Quantum Processor in an HPC Center" was published by researchers at Leibniz Supercomputing Centre, IQM Quantum Computers, and Technical University of Munich. Abstract "As quantum computers mature, they migrate from laboratory environments to HPC centers. This movement enables large-scale deployments,... » read more

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