Many More Hurdles In Heterogeneous Integration

By Laura Peters - 18 Jan, 2024 - Comments: 0

Advanced packaging options continue to stack up in the pursuit of “More than Moore” and higher levels of integration. It has become a place where many high-density interconnects converge, and where many new and familiar problems need to be addressed. The industry’s first foray into fine-pitch multi-die packaging utilized silicon interposers with through-silicon vias (TSVs) to deliver s... » read more

Making Heterogeneous Integration More Predictable

By Ed Sperling - 29 Nov, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss problems and potential solutions in heterogeneous integration with Dick Otte, president and CEO of Promex Industries; Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology; Shekhar Kapoor, senior director of product management at Synopsys; John Park, product management group director in Cadence's Custom I... » read more

Gearing Up For Hybrid Bonding

By Laura Peters - 23 Oct, 2023 - Comments: 2

Hybrid bonding is becoming the preferred approach to making heterogeneous integration work, as the semiconductor industry shifts its focus from 2D scaling to 3D scaling. By stacking chiplets vertically in direct wafer-to-wafer bonds, chipmakers can leapfrog attainable interconnection pitch from 35µm in copper micro-bumps to 10µm or less. That reduces signal delay to negligible levels and e... » read more

Negative-Tone Photosensitive Polymeric Bonding Material To Enable Room Temperature Prebond For Cu/Polymer Hybrid Bonding

By Brewer Science - 18 Oct, 2023 - Comments: 0

An evaluation of a negative-tone i-line photosensitive polymeric bonding material for achieving prebonding in Cu/polymer hybrid bonding at low temperatures via the Cu damascene process. The polymeric material has a Tg≤100∘C ; Young’s modulus of 99 MPa, the dielectric constant of 2.6, and dissipation factor of 0.0016 at 10 GHz. Shear tests revealed a bond shear strength of over 10 MPa when... » read more

Streamlining Failure Analysis Of Chips

By Anne Meixner - 10 Oct, 2023 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss how increasing complexity in semiconductor and packaging technology is driving shifts in failure analysis methods, with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; Mike McIntyre, director of product management in the Enterprise Business Unit at Onto Innovation; Kamran Hak... » read more

Smarter Systems Through Heterogeneous Integration: Highlights From 3D & Systems Summit

By Cassandra Melvin - 25 Jul, 2023 - Comments: 0

It has taken decades of research and development and strong commitment to various industry programs, but the stars are finally aligning for 3D semiconductor systems. No one could have left the 3D & Systems Summit 2023 – held in late June in Dresden – with any doubt that heterogeneous integration, enabled by increasingly mature 3D packaging technologies, is becoming a key driver of the s... » read more

3DICs: Legalizer Techniques For Better Routing Quality, Fewer DRVs, And Reduced Total Slack With Negligible Runtime Impact

By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “On Legalization of Die Bonding Bumps and Pads for 3D ICs” was published by researchers at the Georgia Institute of Technology, NVIDIA Corporation, and the University of Bremen. Abstract "State-of-the-art 3D IC Place-and-Route flows were designed with older technology nodes and aggressive bonding pitch assumptions. As a result, these flows fail to honor the widt... » read more

Big Changes Ahead In Power Delivery, Materials, And Interconnects

By Laura Peters - 22 Mar, 2023 - Comments: 0

Part one of this forecast looked at evolving transistor architectures and lithography platforms. This report examines revolutions in interconnects and packaging. When it comes to device interconnects, it’s hard to beat copper. Its low resistivity and high reliability have served the industry exceedingly well as both on-chip interconnect and wires between chips. But in logic chips, with int... » read more

Advanced Packaging for High-Bandwidth Memory: Influences of TSV size, TSV Aspect Ratio And Annealing Temperature

By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A technical paper titled "Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications" was published by researchers at National Yang Ming Chiao Tung University. Abstract: "The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for ... » read more

The Path To Known Good Interconnects

By Laura Peters - 19 Jan, 2023 - Comments: 1

Chiplets and heterogenous integration (HI) provide a compelling way to continue delivering improvements in performance, power, area, and cost (PPAC) as Moore’s Law slows, but choosing the best way to connect these devices so they behave in consistent and predictable ways is becoming a challenge as the number of options continues to grow. More possibilities also bring more potential interac... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?