New BEOL/MOL Breakthroughs?

By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

Modeling On-Chip Variation At 10/7nm

By Ann Mutschler - 14 Jun, 2017 - Comments: 1

Simulation, a workhorse tool for semiconductor design, is running out of steam at 10/7nm. It is falling behind on chips with huge gate counts and an enormous number of possible interactions between all the different functions that are being crammed onto a die. At simulation's root is some form of SPICE, which has served as its underpinnings ever since SPICE was first published 44 years ago. ... » read more

2.5D, ASICs Extend to 7nm

By Mark LaPedus - 13 Jun, 2017 - Comments: 2

The leading-edge foundry market is heating up. For example, GlobalFoundries, Intel, Samsung and TSMC have recently announced their new and respective processes. The new processes from vendors range anywhere from 10nm to 4nm, although the current battle is taking place at 10nm and/or 7nm. In fact, one vendor, GlobalFoundries, this week will describe more details about its previously-announced... » read more

System Bits: June 6

By Ann Mutschler - 06 Jun, 2017 - Comments: 0

Silicon nanosheet-based builds 5nm transistor To enable the manufacturing of 5nm chips, IBM, GLOBALFOUNDRIES, Samsung, and equipment suppliers have developed what they say is an industry-first process to build 5nm silicon nanosheet transistors. This development comes less than two years since developing a 7nm test node chip with 20 billion transistors. Now, they’ve paved the way for 30 billi... » read more

Leasing and Rental in T&M

By Jeff Dorsch - 05 Jun, 2017 - Comments: 0

Buying a high-end oscilloscope or a brand-new logic analyzer may be a tall order financially for small companies. In such cases, leasing or renting an expensive test instrument can be an affordable alternative. Having reliable test and measurement equipment is vital to product development in electronics. National Instruments has built a billion-dollar business on offering instrument hardware... » read more

IIoT Grows, But So Do Risks

By Jeff Dorsch - 04 May, 2017 - Comments: 1

By Jeff Dorsch & Ed Sperling After years of fitful progress, [getkc id="78" kc_name="Industrial Internet of Things"] technology is gaining adoption on the factory floor, in the electrical power grid, and other areas that could do with greater amounts of data analysis and insights from a connected ecosystem. AT&T, General Electric, IBM, Verizon Communications, and other large ... » read more

Can Formal Replace Simulation?

By Brian Bailey - 01 May, 2017 - Comments: 1

A year ago, [getentity id="22147" comment="Oski Technology"] achieved something that had never happened before. It brought together 15 of the top minds in [getkc id="33" kc_name="formal verification"] deployment and sat them down in a room to discuss the problems and issues they face and the ways in which they are attempting to solve those problems. Semiconductor Engineering was there to record... » read more

The Week In Review: IoT

By Jeff Dorsch - 28 Apr, 2017 - Comments: 0

Finance SENSORO reports receiving $18 million in Series B funding from Robert Bosch Venture Capital, Sumitomo, and Tsing Capital. Nokia Growth Partners provided $10 million in first-round financing two years ago. SENSORO, which provides Internet of Things sensor devices and network technology, was established in 2013 as part of the Microsoft Accelerator program. Daylight Investors of Los An... » read more

The Rise Of Parallelism

By Ed Sperling - 27 Apr, 2017 - Comments: 1

Parallel computing is an idea whose time has finally come, but not for the obvious reasons. Parallelism is a computer science concept that is older Moore's Law. In fact, it first appeared in print in a 1958 IBM research memo, in which John Cocke, a mathematician, and Daniel Slotnick, a computer scientist, discussed parallelism in numerical calculations. That was followed eight years later by... » read more

22nm Process War Begins

By Mark LaPedus - 23 Apr, 2017 - Comments: 1

Many foundry customers at the 28nm node and above are developing new chips and are exploring the idea of migrating to 16nm/14nm and beyond. But for the most part, those companies are stuck because they can’t afford the soaring IC design costs at advanced nodes. Seeking to satisfy a potential gap in the market, [getentity id="22819" comment="GlobalFoundries"], [getentity id="22846" e_name="... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: IBM

New BEOL/MOL Breakthroughs?

Modeling On-Chip Variation At 10/7nm

2.5D, ASICs Extend to 7nm

System Bits: June 6

Leasing and Rental in T&M

IIoT Grows, But So Do Risks

Can Formal Replace Simulation?

The Week In Review: IoT

The Rise Of Parallelism

22nm Process War Begins

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Entities, people and technologies explored