The Week In Review: Manufacturing

Fab tool trade theft; TSMC vendor awards; 10nm/7nm; nano ICs.


Fab tools and test
Four former employees at Applied Materials were charged by the U.S. for allegedly trying to steal the company’s own fab tool technology designs, according to a report from Bloomberg and others. The former employees were allegedly trying to sell the technology to a Chinese startup that would compete against Applied, according to the report.

The former employees–Liang Chen, Donald Olgado, Wei-Yung Hsu, and Robert Ewald–were allegedly accused of a plan to use stolen information for sale to a startup, according to the report. If convicted, they face up to 10 years imprisonment and a $250,000 fine for each charge, according to the Mercury News.

According to the Mercury News, “Chen, 52 was a corporate vice president and general manager of the alternative energy products division; Olgado, 54 was a managing director of engineering within the product business group; Hsu, 57, was a vice president and general manager within the semiconductor LED division; and Ewald, 60, was a director of the energy and environmental systems within the alternative energy products division.”

The charges, which can be read here, were issued in an indictment handed down on Nov. 30.


TSMC held its 17th annual Supply Chain Management forum and presented awards for its various tool and materials suppliers in 2017. The awards reflect its suppliers’ contributions to TSMC’s 10nm capacity ramp and technology development at 7nm and beyond.

Twelve suppliers were recognized by TSMC, including the following: Applied Materials (technology collaboration); ASM International (CVD equipment); ASML (EUV collaboration); EBARA (CMP); Hitachi Kokusai (furnace); Lam (etch); Tokyo Electron Ltd. (production ramp support); Fujifilm (CMP material); HOYA (mask blanks); Shin-Etsu (silicon wafers); SUMCO(silicon wafers); and Tokyo Ohka Kogyo (lithography materials).


Expanding its efforts in the display equipment sector, TEL has begun accepting orders for the Betelex 1800 PICP, a dry etch system capable of processing sixth generation glass substrates (1500mm x 1850mm). The tool supports up to five chambers, featuring a planar inductively coupled plasma mode for high-resolution processes.

Intel has reduced its stake in ASML from 9.96% to 4.96%, according to a report from Reuters. Several years ago, Intel, Samsung and TSMC invested in ASML in order to propel the development of extreme ultraviolet (EUV) lithography.

Bad news for Veeco. “A provincial high court in China ruled that Veeco must stop making and selling its EPIK 700 model in China, based on alleged infringements of patents held by AMEC, a competitor to Veeco in China,” according to a report from KeyBanc Capital Markets. “We do not view this announcement as materially impacting our estimates because Veeco is now primarily selling its next-generation MOCVD tool, the EPIK 868, in China. The ruling does, however, highlight the increasingly competitive environment, in which new entrants such as AMEC have taken meaningful share, and how Veeco’s response has been to claw back share at the cost of very low margins in a growing market.”

Advantest has introduced two new modules that enable its T2000 IPS system to test high-voltage and high-power devices used in power trains of electric vehicles (EV/HV). The new modules enable massively parallel, high-performance testing by leveraging Advantest’s multifunctional pin design. In addition, Advantest has launched its HA7300 stimulus test cell, a test solution for differential pressure sensors in automobile designs.

National Instruments (NI) has announced MAC layer support for its LabVIEW Communications 802.11 Application Framework. Wireless researchers can take advantage of the new multiuser MAC layer enhancements to the 802.11 Application Framework to go beyond the PHY layer to address complex network-level problems that must be solved to make 5G a reality.

SEMI reported that worldwide semiconductor manufacturing equipment billings reached $14.3 billion for the third quarter of 2017. The figure set an all-time record for quarterly billings, exceeding the record level set in the second quarter of this year. Billings for the most recent quarter are 2% higher than the second quarter of 2017 and 30% higher than the same quarter a year ago.

United Microelectronics Corp. (UMC) announced that its Singapore-based Fab 12i has been awarded the Water Efficiency Award by the Singapore Ministry of Environment and Water Resources. Fab 12i became the only Singapore fab to win the award from the wafer fabrication sector.

GlobalFoundries and Ayar Labs, a startup bringing optical input/output (I/O) to silicon chips, have announced a collaboration to co-develop and commercialize silicon photonic technology solutions. The companies will develop and manufacture Ayar’s CMOS optical I/O technology, using GF’s 45nm CMOS fabrication process.

Broadcom continues its unsolicited efforts to acquire Qualcomm. Broadcom has notified Qualcomm of its intention to nominate a slate of 11 independent individuals for election to Qualcomm’s board. Qualcomm has rejected the bid.

Silicon Labs will acquire Sigma Designs for $7.05 per share in a cash transaction valued at approximately $282 million, subject to certain closing conditions. Sigma Designs provides solutions for the connected home including Z-Wave, a leading Internet of Things (IoT) technology for smart home solutions.

IBM has unveiled its next-generation Power Systems Servers incorporating its new POWER9 processor. Built for compute-intensive AI workloads, the new POWER9 systems are capable of improving the training times of deep learning frameworks by nearly 4x, allowing enterprises to build more accurate AI applications faster. The new POWER9-based AC922 Power Systems are the first to embed PCI-Express 4.0, next-generation NVIDIA NVLink and OpenCAPI, which combined can accelerate data movement, calculated at 9.5x faster than PCI-E 3.0 based x86 systems.

IEDM news
At this week’s IEEE International Electron Devices Meeting (IEDM), GlobalFoundries and Intel squared off and presented papers on their new logic processes. Intel presented more details about its previously-announced 10nm finFET technology, while GlobalFoundries discussed its 7nm finFET process.

Amid the ongoing ramp of 16/14nm processes in the market, the industry is now gearing up for the next nodes. In fact, GlobalFoundries, Intel, Samsung and TSMC are racing each other to ship 10nm and/or 7nm technologies.

Also at the event, Imec presented separate papers with Applied Materials and Lam Research.

In one paper, Imec and Applied demonstrated the first functional ring oscillators based on a lateral gate-all-around (GAA) nanowire device. Lateral GAA MOSFETs based on nanowires and/or nanosheets are promising candidates to replace finFETs at 5nm/3nm.

Imec and Applied fabricated a vertically stacked GAA FET with nanowires. The device incorporated in-situ doped source-drain stressors and dual-work function metal gates. It demonstrated good electrostatic control down to the minimal gate length of 24nm with a steep slope of 65mV/dec for NMOS and 75mV/dec for PMOS.

Compared to previous work, Imec and Applied implemented process improvements for shallow trench isolation (STI), source-drain (S/D) epitaxy, nanowire/nanosheet release and Vt tuning. “The first process optimization is the implementation of a SiN shallow trench isolation (STI) liners which suppresses oxidation-induced fin deformation and improves the shape control of the nanowire or nanosheet,” according to Imec. “Secondly, (Applied’s Selectra atomic layer etch tool) was used to enable nanowire/nanosheet release and inner spacer cavity formation with high selectivity and without causing silicon reflow. Finally, for the first time, ring oscillator circuits were reported based on stacked silicon nanowire FETs, including dual work function metal gates for threshold voltage control.”

Then, in a separate paper, Imec, Lam Research and KU Leuven presented a possible follow-on to the lateral GAA FETs—the vertical nanowire FET. The vertical nanowire FET from Imec, Lam and KU also includes vertical nanosheets with III-V materials (InGaAs).

In the flow, a pattern is formed on a structure using e-beam lithography. A hard mask opening is etched. Then, the pillar etch steps are done on the some tool. The vertical nanowire diameters range from 25nm to 75nm in arrays from 1 to 100 nanowires, according to the paper. The vertical nanosheet cross sections range from 37nm x 480nm and 18nm x 460nm in arrays from 1 to 70 nanosheets, according to the paper.

“With a VLSI compatible process flow, we have demonstrated top-down fabricated devices with record performance in terms of SSmin, GmMAX and ION,” according to the paper.

Also at IEDM, Leti, a research institute of CEA Tech, has integrated hybrid III-V silicon lasers on 200mm wafers using a standard CMOS process flow.

This paves the way to transitioning away from 100mm wafers and a process based on bulk III-V technology, which requires contacts with noble metals and lift-off based patterning. The fabrication flow is planar and compatible with large-scale integration on silicon-photonic circuits.

The integration required managing a thick silicon film (500nm) for the hybrid laser, and a thinner one (300nm) for the baseline silicon-photonic platform, according to Leti. This required locally thickening the silicon by adding 200nm of amorphous silicon via a damascene process, according to Leti. The laser can be integrated on a mature silicon photonic platform with a modular approach that does not compromise the baseline process performance.

“Silicon-photonic technologies are becoming more mature, but the main limitation of these platforms is the lack of an integrated light source,” said Bertrand Szelag from Leti. “This project showed that a laser can be integrated on a mature silicon-photonic platform with a modular approach that does not compromise baseline process performances. We demonstrated that the entire process can be done in a standard CMOS fabrication line with conventional process and materials, and that it is possible to integrate all the photonic building blocks at large scale.”

Leave a Reply

(Note: This name will be displayed publicly)