tag: IBM

E-beam Vs. Optical Inspection
By Mark LaPedus - 11 Jul, 2016 - Comments: 0

The wafer inspection business is heating up as chipmakers encounter new and tiny killer defects in advanced devices. Last month ASML Holding entered into an agreement to acquire Hermes Microvision (HMI), the world’s largest e-beam inspection vendor, for $3.1 billion. The proposed move propelled ASML into the e-beam wafer inspection market. In addition, [getentity id="22817" e_name="Appl... » read more

Will Open-Source Work For Chips?
By Brian Bailey - 30 Jun, 2016 - Comments: 2

Open source is getting a second look by the semiconductor industry, driven by the high cost of design at complex nodes along with fragmentation in end markets, which increasingly means that one size or approach no longer fits all. The open source movement, as we know it today, started in the 1980s with the launch of the GNU project, which was about the time the electronic design automation (... » read more

Interconnect Challenges Rising
By Mark LaPedus - 27 Jun, 2016 - Comments: 1

Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next. At 10nm and beyond, IC vendors are determined to scale the two main parts of the [getkc id="185" kc_name="finFET"] structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects ... » read more

The Road To 5nm
By Ed Sperling - 23 Jun, 2016 - Comments: 1

There is strong likelihood that enough companies will move to 7nm to warrant the investment. How many will move forward to 5nm is far less certain. Part of the reason for this uncertainty is big-company consolidation. There are simply fewer customers left who can afford to build chips at the most advanced nodes. Intel bought Altera. Avago bought Broadcom. NXP bought Freescale. GlobalFoundrie... » read more

Next Challenge: Contact Resistance
By Mark LaPedus - 23 Jun, 2016 - Comments: 0

In chip scaling, there is no shortage of challenges. Scaling the finFET transistor and the interconnects are the biggest challenges for current and future devices. But now, there is another part of the device that’s becoming an issue—the contact. Typically, the contact doesn’t get that much attention, but the industry is beginning to worry about the resistance in the contacts, or conta... » read more

Photonics Moves Closer To Chip
By Ed Sperling - 20 Jun, 2016 - Comments: 0

Silicon photonics is resurfacing after more than a decade in the shadows, driven by demands to move larger quantities of data faster, using extremely low power and with minimal heat. Until recently, much of the attention in photonics focused on moving data between servers and storage. Now there is growing interest at the PCB level and in heterogeneous multi-chip packages. Government, academi... » read more

Big Data Meets Chip Design
By Ann Mutschler - 16 Jun, 2016 - Comments: 0

The amount of data being handled in chip design is growing significantly at each new node, prompting chipmakers to begin using some of the same concepts, technologies and algorithms used in data centers at companies such as Google, Facebook and GE. While the total data sizes in chip design are still relatively small compared with cloud operations—terabytes per year versus petabytes and exa... » read more

How To Build Systems In Package
By Ed Sperling - 15 Jun, 2016 - Comments: 0

The semiconductor industry is racing to define a series of road maps for semiconductors to succeed the one created by the ITRS, which will no longer be updated, including a brand new one focused on heterogeneous integration. The latest entry will establish technology targets for integration of heterogeneous multi-die devices and systems. It has the support of IEEE's Components, Packaging and... » read more

Pathfinding Beyond FinFETs
By Paula Doe - 13 Jun, 2016 - Comments: 0

Though the industry will likely continue to find ways to extend CMOS finFET technology further than we thought possible, at some point in the not-so-distant future, making faster, lower power ICs will require more disruptive changes. For something that could be only five to seven years out, there’s a daunting range of contending technologies. Improvements through the process will help, from E... » read more

DAC Day Four: Excitement And Risk
By Brian Bailey - 09 Jun, 2016 - Comments: 0

One thing that was new to DAC this year, was an art exhibit. These were pieces of artwork related to our industry, such as chip plots, or more abstract ideas based on design data or analyses. They received many more entrants than their wildest dreams and had to choose a winner from over 80 pieces, but the grand prize was won by a 3D model of a finFET by David Freid of Coventor. This piece was ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy