EDA’s Clouded Future


There was a time, not that long ago, when chip design and EDA tools consumed some of the largest data centers with tens of thousands of machines and single datasets that consumed more than a hard disk could hold. The existing IT capabilities of the times were stretched to their limits. But while design sizes grew, other aspects of the flow did not develop as fast. “This has been driven by ... » read more

DoD Scratches Its Head Over Foundry Security


When the GlobalFoundries deal with IBM to acquire its foundries closes, as it is slated to sometime during 2015, the U.S. Department of Defense has a small problem on its hands. Military programs no longer will have access to a trusted fab to manufacture semiconductors. How do you ensure that the foundry did not modify or alter your design, add backdoor access or implement a remote control mech... » read more

3 Ways To Reload Moore’s Law


The electronics revolution has been enabled because the cost and power per transistor has decreased 30% per year for the last 30 years — a fact usually associated with Moore's Law. This has been accomplished by simply reducing the transistor size while offsetting increased costs of equipment and mask levels, and by increased productivity from improved yield, throughput and wafer size. This... » read more

Speeding Up E-beam Inspection


Wafer inspection, the science of finding killer defects in chips, is reaching a critical juncture. Optical inspection, the workhorse technology in the fab, is being stretched to the limit at advanced nodes. And e-beam inspection can find tiny defects, but it remains slow in terms of throughput. So to fill the gap, the industry has been working on a new class of multiple beam e-beam inspectio... » read more

Semiconductor R&D Crisis?


Research and development is a sometimes forgotten but critical element in the semiconductor industry. The delicate R&D ecosystem enables many of the key breakthroughs in the business. But there could be a troubling trend, if not a crisis, brewing on two fronts in the R&D arena. On one front, R&D costs for semiconductor technologies are escalating at each node. Higher R&D costs are not only ... » read more

The Week In Review: Manufacturing


At an event, Samsung rolled out its 10nm finFET technology. The company also showed a 300mm wafer with 10nm finFET transistors. "We have silicon-based PDKs out," said Kelvin Low, senior director of foundry marketing for Samsung. Samsung plans to move into production with its 10nm finFET technology by the end of 2016, he said. IC Insights released its chip rankings in terms of sales in the fi... » read more

Week 50: It’s Not Just A Technical Conference, It’s An Ecosystem


While our free “I love DAC” registration comes to an end this week, there are still a few weeks left to register for the full conference, the designer and IP track, or one of the many co-located events at DAC (see below). Over the last year I’ve been reminded often about the unique niche occupied by DAC. Just last week a good friend was trying to find an industry event in the greater EDA ... » read more

The Bumpy Road To 10nm FinFETs


Foundry vendors are currently ramping up their 16nm/14nm [getkc id="185" kc_name="finFET"] processes in the market. Vendors are battling each other for business in the arena, although the migration from planar to finFETs is expected to be a slow and expensive process. Still, despite the challenges at 16nm/14nm, vendors are gearing up for the next battle in the foundry business—the 10nm nod... » read more

One-On-One: Thomas Caulfield


Semiconductor Engineering sat down to talk about fabs, process technology and the equipment industry with Thomas Caulfield, senior vice president and general manager of Fab 8 at [getentity id="22819" comment="GlobalFoundries"]. Located in Saratoga County, N.Y., Fab 8 is GlobalFoundries’ most advanced 300mm wafer fab. What follows are excerpts of that discussion. SE: Last year, GlobalFoundr... » read more

Brain-Inspired Computing


Approaching power/performance tradeoffs from an architectural perspective is essential given the complexities of today’s SoCs. And beyond some traditional techniques that I discussed in a recent article, Bernard Murphy, CTO at Atrenta mentioned that there is currently a lot of buzz about using non-Von Neumann architectures — especially for recognition functions (voice, image and text). ... » read more

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