The Week In Review: Manufacturing & Design

By Mark LaPedus - 13 Dec, 2013 - Comments: 0

Tensions between the U.S. and China are growing. In a research report, Gus Richard, an analyst at Piper Jaffray, said: “The technology sector is being impacted by U.S./Chinese tensions over cybersecurity. The combination of Huawei being blocked from doing business in the United States and the Snowden affair are impacting U.S. tech companies' prospects in China. China’s state-run media ident... » read more

Fastest Computers On The Planet

By Barry Pangrle - 05 Dec, 2013 - Comments: 0

The latest Green500 list (Excel spreadsheet here) was just released at the end of last month and heterogeneous systems now own the top of the list. The Top 10 systems all use a combination of Intel Xeon (mostly E5) processors paired with NVIDIA K20s. There are now 6 systems listed that have broken the 3,000 MFLOPS/W barrier and TSUBAME-KFC, belonging to the Tokyo Institute of Technology’s GSI... » read more

Do Students Need More Formal Education?

By Brian Bailey - 21 Nov, 2013 - Comments: 0

A few weeks ago, some of the top researchers and practitioners in the area of formal methods converged on Portland, Oregon. The event was the annual Formal Methods in Computer-Aided Design (FMCAD) conference and Semiconductor Engineering attended the panel titled “Teaching Formal Methods: Needs, Challenges, Experiences, and Opportunities.” Panelists included: Jason Baumgartner, formal verif... » read more

Tunnel FETs Emerge In Scaling Race

By Mark LaPedus - 14 Nov, 2013 - Comments: 2

Traditional CMOS scaling will continue for the foreseeable future, possibly to the 5nm node and perhaps beyond, according to many chipmakers. In fact, chipmakers already are plotting out a path toward the 5nm node, but needless to say, the industry faces a multitude of challenges along the road. Presently, the leading transistor candidates for 5nm are the usual suspects—III-V finFETs; gate... » read more

What’s After 10nm?

By Mark LaPedus - 14 Nov, 2013 - Comments: 0

For some time, chipmakers have roughly doubled the transistor count at each node, while simultaneously cutting the cost by around 29%. IC scaling, in turn, enables faster and lower cost chips, which ultimately translates into cheaper electronic products with more functions. Consumers have grown accustomed to the benefits of Moore’s Law, but the question is for how much longer? Chips based ... » read more

Momentum Builds For Monolithic 3D ICs

By Mark LaPedus - 14 Nov, 2013 - Comments: 1

The 2.5D/3D chip market is heating up on several fronts. On one front, stacked-die using through-silicon vias (TSVs) is taking root. In a separate area, Samsung is sampling the world’s first 3D NAND device, with Micron and SK Hynix expected to follow suit. And now, there is another technology generating steam—monolithic 3D integrated circuits. In stacked-die, bare die are connected using... » read more

Atoms, ARMs, ARCs, Andes…And All The Rest

By Brian Bailey - 07 Nov, 2013 - Comments: 0

There was a time when nobody believed Intel processors would be replaced with any other device. Intel commanded the processor market. Rich Wawrzyniak, senior analyst for ASIC SoC at Semico Research, noted this was not always the case. In the early days of the PC there were many contenders and most people thought that Motorola would win because they had more money behind them. Ultimately, Intel ... » read more

System Bits: Nov. 5

By Brian Bailey - 05 Nov, 2013 - Comments: 0

Silicon Photonics And Graphene The industry is looking towards silicon photonics that will increase the rate at which electronic systems can communicate with each other and reduce power consumption. Researchers at MIT, Columbia University and IBM’s T. J. Watson Research Center are already a few steps beyond the traditional attempts to build optical components using materials such as Gallium ... » read more

Manufacturing Bits: Oct. 1

By Mark LaPedus - 01 Oct, 2013 - Comments: 0

Nanoimprint Foundry Singapore’s A*STAR’s Institute of Materials Research and Engineering (IMRE) and its partners have launched a new R&D foundry using nanoimprint lithography. The so-called Nanoimprint Foundry is a collaboration between several entities, such as IMRE, Toshiba Machines, EV Group, NTT, NIL Technology, Kyodo International, Micro Resist Technology, Nanoveu and Solves In... » read more

Rethinking The Data Center

By Ed Sperling - 27 Sep, 2013 - Comments: 0

Ever since the introduction of the PC, the biggest challenge in computing has been more about getting software to take advantage of multiple processors or cores than getting the chips to run faster. Ironically, this issue was solved decades ago inside of data centers. Enterprise applications, built on databases, have always been relatively easy to parse so that individual pieces can be run sepa... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?