Chip Industry Week In Review


Europe's top court ruled in Intel's favor, voiding a $1.1 billion fine imposed by the European Union and dismissing charges of anti-competitive behavior. IBM released yield benchmarks for high-NA EUV, which serve as proof points that the newest advanced litho equipment will enable scaling beyond the 2nm process node. Also on the lithography front, Nikon is developing a maskless digital litho... » read more

Review of Automatic EM Image Algorithms for Semiconductor Defect Inspection (KU Leuven, Imec)


A new technical paper titled "Electron Microscopy-based Automatic Defect Inspection for Semiconductor Manufacturing: A Systematic Review" was published by researchers at KU Leuven and imec. Abstract: "In this review, automatic defect inspection algorithms that analyze Electron Microscope (EM) images of Semiconductor Manufacturing (SM) products are identified, categorized, and discussed. Thi... » read more

Chip Industry Week In Review


Arm joined forces with Korea's Samsung Foundry, ADTechnology, and Rebellions to create a CPU chiplet platform for AI training and inference. The new chiplet will be based on Samsung's 2nm gate-all-around technology. Intel and AMD, arch competitors for decades, formed an x86 ecosystem advisory group to collaborate on architectural interoperability and simplify software development. Samsung... » read more

Metrology Advances Step Up To Sub-2nm Device Node Needs


Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

Chip Industry Week In Review


Imec announced a new automotive chiplet consortium to evaluate which different architectures and packaging technologies are best for automotive applications. Initial members includes Arm, ASE, Cadence, Siemens, Synopsys, Bosch, BMW, Tenstorrent, Valeo, and SiliconAuto. Imec also launched star, a global network bringing together automotive and semiconductor innovators to address technological c... » read more

Challenges In Reducing Wireless Latency


A new and much faster version of Wi-Fi is beginning to infiltrate the IoT market, reducing latency that has begun to creep up as more data is generated, processed, and moved wirelessly from one device to another. An estimated 20 billion connected devices are currently in use. Over the next several years, devices will start to include faster wireless connectivity, enabling more rapid transfer... » read more

Government Chip Funding Spreads Globally


This is the first in a series of articles tracking government chip investments. See part two for Americas-focused funding and part three for the UK and EMEA, and part four for Asia. Countries around the world are ramping up investments into their semiconductor industries as part of new or existing approaches. The increased government activity stems from growing awareness of the strategic imp... » read more

Preparing For Ferroelectric Devices


The discovery of ferroelectricity in materials that are compatible with integrated circuit manufacturing has sparked a wave of interest in ferroelectric devices. Ferroelectrics are materials with a permanent polarization, the direction of which can be switched by an applied field. This polarization can be used to raise or lower the threshold voltage of a transistor, as in FeFETs, or it can c... » read more

Chip Industry Technical Paper Roundup: Oct. 1


New technical papers recently added to Semiconductor Engineering’s library: [table id=360 /] More ReadingTechnical Paper Library home » read more

Fine-Grained Functional Partitioning For Low Level SRAM Cache in 3D-IC designs (imec)


A new technical paper titled "Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs" was published by researchers at imec. "We propose a partitioning of low-level (faster access) caches in 3D using an Array Under CMOS (AuC) technology paradigm. Our study focuses on partitioning and optimization of SRAM bit-cells and peripheral circuits, enabling heterogeneous ... » read more

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