Chip Industry Week In Review


By Jesse Allen, Linda Christensen, and Liz Allan.  The Biden administration plans to invest more than $5B  for semiconductor R&D and workforce support, including in the National Semiconductor Technology Center (NSTC), as part of the rollout of the CHIPS Act. Today's announcement included at least hundreds of millions for the NSTC workforce efforts, including creating a Workforce Cente... » read more

Evaluation of Cache Replacement Policies Using Various Typical Simulation Approaches


A technical paper titled “Improving the Representativeness of Simulation Intervals for the Cache Memory System” was published by researchers at Complutense University of Madrid, imec, and KU Leuven. Abstract: "Accurate simulation techniques are indispensable to efficiently propose new memory or architectural organizations. As implementing new hardware concepts in real systems is often not... » read more

Many More Hurdles In Heterogeneous Integration


Advanced packaging options continue to stack up in the pursuit of “More than Moore” and higher levels of integration. It has become a place where many high-density interconnects converge, and where many new and familiar problems need to be addressed. The industry’s first foray into fine-pitch multi-die packaging utilized silicon interposers with through-silicon vias (TSVs) to deliver s... » read more

Money Pours Into New Fabs And Facilities


Fabs, packaging, test and assembly, and R&D all drew major funding in 2023. Companies poured money into offshore locations, such as India and Malaysia, to access a larger workforce and lower costs, while also partnering with governments to secure domestic supply chains amid ongoing geopolitical turmoil. Looking ahead, artificial intelligence (AI), quantum computing, and data applications... » read more

Research Bits: Jan. 2


Synaptic transistor Researchers from Northwestern University, Boston College, and MIT developed a synaptic transistor that simultaneously processes and stores information similar to the human brain. The team said the transistor goes beyond simple machine learning tasks to categorize data and is capable of performing associative learning. The new device is stable at room temperatures. It als... » read more

A New Approach For Sensor Design


Pawel Malinowski, program manager at imec, sat down with Semiconductor Engineering to discuss what's changing in sensor technology and why. What follows are excerpts of that discussion. SE: What's next for sensor technology? Malinowski: We are trying to find a new way of making image sensors because we want to get out of the limitations of silicon photodiodes. Silicon is a perfect materi... » read more

Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan More than 1 billion generative AI smartphones are expected be shipped during 2024 to 2027, reports Counterpoint. The share of GenAI smartphones will be 4% of the market in 2023 and is likely to double in 2024, with Samsung capturing half the market, followed by Chinese OEMs. By 2027, GenAI smartphones could account for 40% of the market. Global ... » read more

Chip Industry Technical Paper Roundup: Dec 18


New technical papers added to Semiconductor Engineering’s library this week. [table id=176 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan Synopsys acquired Imperas, pushing further into the RISC-V world with Imperas' virtual platform technology for verifying and emulating processors. Synopsys has been building up its RISC-V portfolio, starting with ARC-V processor IP and a full suite of tools introduced last month. The first high-NA EUV R&D center in the U.S. will be built at... » read more

A Framework For Improving Current Defect Inspection Techniques For Advanced Nodes


A technical paper titled “Improved Defect Detection and Classification Method for Advanced IC Nodes by Using Slicing Aided Hyper Inference with Refinement Strategy” was published by researchers at Ghent University, imec, and SCREEN SPE. Abstract: "In semiconductor manufacturing, lithography has often been the manufacturing step defining the smallest possible pattern dimensions. In recent ... » read more

← Older posts Newer posts →