Chip Industry Technical Paper Roundup: May 28


New technical papers recently added to Semiconductor Engineering’s library: [table id=434 /] Find more semiconductor research papers here. » read more

Energy-Aware DL: The Interplay Between NN Efficiency And Hardware Constraints (Imperial College London, Cambridge)


A new technical paper titled "Energy-Aware Deep Learning on Resource-Constrained Hardware" was published by researchers at Imperial College London and University of Cambridge. Abstract "The use of deep learning (DL) on Internet of Things (IoT) and mobile devices offers numerous advantages over cloud-based processing. However, such devices face substantial energy constraints to prolong batte... » read more

Chip Industry Technical Paper Roundup: Apr. 7


New technical papers recently added to Semiconductor Engineering’s library: [table id=419 /] Find more semiconductor research papers here. » read more

Chip Industry Technical Paper Roundup: Jan. 28


New technical papers recently added to Semiconductor Engineering’s library: [table id=400 /] Find all technical papers here. » read more

Analog Accelerator For AI/ML Training Workloads Using Stochastic Gradient Descent (Imperial College London)


A new technical paper titled "Learning in Log-Domain: Subthreshold Analog AI Accelerator Based on Stochastic Gradient Descent" was published by researchers at Imperial College London. Abstract "The rapid proliferation of AI models, coupled with growing demand for edge deployment, necessitates the development of AI hardware that is both high-performance and energy-efficient. In this paper, w... » read more

Chip Industry Technical Paper Roundup: Oct. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=375 /] More Reading Chip Industry Week In Review Intel’s EU court win; high-NA benchmarks and new maskless litho; SiC down, GaN up; Natcast’s plan; Xiaomi’s 3nm chip; semi tax credit rules; RISC-V; lithium mine; AI-edge expansion. Technical Paper Library home » read more

Formally Modeling and Verifying CXL Cache Coherence (Imperial College London)


A new technical paper titled "Formalising CXL Cache Coherence" was published by researchers at Imperial College London. Abstract "We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on the prose English spec... » read more

Chip Industry Technical Paper Roundup: Sept. 17


New technical papers recently added to Semiconductor Engineering’s library: [table id=356 /] More ReadingTechnical Paper Library home » read more

Scalable Fabrication of Graphene FETs on Non-Planar Surfaces (Imperial College London)


A new technical paper titled "Fabrication of graphene field effect transistors on complex non-planar surfaces" was published by researchers at Imperial College London. Abstract "Graphene field effect transistors (GFETs) are promising devices for biochemical sensing. Integrating GFETs onto complex non-planar surfaces could uncap their potential in emerging areas of wearable electronics, such... » read more

Chip Industry Technical Paper Roundup: July 16


New technical papers recently added to Semiconductor Engineering’s library. [table id=244 /] More ReadingTechnical Paper Library home   » read more

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