Chip Industry Technical Paper Roundup: Oct. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=375 /] More Reading Chip Industry Week In Review Intel’s EU court win; high-NA benchmarks and new maskless litho; SiC down, GaN up; Natcast’s plan; Xiaomi’s 3nm chip; semi tax credit rules; RISC-V; lithium mine; AI-edge expansion. Technical Paper Library home » read more

Formally Modeling and Verifying CXL Cache Coherence (Imperial College London)


A new technical paper titled "Formalising CXL Cache Coherence" was published by researchers at Imperial College London. Abstract "We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on the prose English spec... » read more

Chip Industry Technical Paper Roundup: Sept. 17


New technical papers recently added to Semiconductor Engineering’s library: [table id=356 /] More ReadingTechnical Paper Library home » read more

Scalable Fabrication of Graphene FETs on Non-Planar Surfaces (Imperial College London)


A new technical paper titled "Fabrication of graphene field effect transistors on complex non-planar surfaces" was published by researchers at Imperial College London. Abstract "Graphene field effect transistors (GFETs) are promising devices for biochemical sensing. Integrating GFETs onto complex non-planar surfaces could uncap their potential in emerging areas of wearable electronics, such... » read more

Chip Industry Technical Paper Roundup: July 16


New technical papers recently added to Semiconductor Engineering’s library. [table id=244 /] More ReadingTechnical Paper Library home   » read more

RTL Optimization Via Verified E-Graph Rewriting (Intel, Imperial College London)


A technical paper titled “ROVER: RTL Optimization via Verified E-Graph Rewriting” was published by researchers at Intel Corporation and Imperial College London. Abstract: "Manual RTL design and optimization remains prevalent across the semiconductor industry because commercial logic and high-level synthesis tools are unable to match human designs. Our experience in industrial datapath des... » read more

Chip Industry Technical Paper Roundup: April 30


These new technical papers were recently added to Semiconductor Engineering’s library. [table id=222 /] Find more technical papers here. » read more

Merging Power and Arithmetic Optimization Via Datapath Rewriting (Intel, Imperial College London)


A new technical paper titled "Combining Power and Arithmetic Optimization via Datapath Rewriting" was published by researchers at Intel Corporation and Imperial College London. Abstract: "Industrial datapath designers consider dynamic power consumption to be a key metric. Arithmetic circuits contribute a major component of total chip power consumption and are therefore a common target for p... » read more

Chip Industry Technical Paper Roundup: Dec 18


New technical papers added to Semiconductor Engineering’s library this week. [table id=176 /] More ReadingTechnical Paper Library home » read more

A Polymer-Free Technique For Assembling Van Der Waals Heterostructures Using Flexible Si Nitride Membranes


A technical paper titled “Clean assembly of van der Waals heterostructures using silicon nitride membranes” was published by researchers at University of Manchester, Imperial College London, National Institute for Materials Science (Japan), and University of Lancaster. Abstract Van der Waals heterostructures are fabricated by layer-by-layer assembly of individual two-dimensional mater... » read more

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