Study Of Bondable Laser Release Material Using 355nm Energy To Facilitate RDL-First And Die-First Fan-Out Wafer-Level Packaging (FOWLP)

By Brewer Science - 18 May, 2022 - Comments: 0

A thorough evaluation on selecting a bondable laser release material for redistribution layer (RDL)-first and die-first fan-out wafer-level packaging (FOWLP) is presented in this article. Four laser release materials were identified based on their absorption coefficient at 355 nm. In addition, all four of these materials possess thermal stability above 350 °C and pull-off adhesion on a Ti/Cu l... » read more

Week In Review: Design, Low Power

By Jesse Allen - 04 Mar, 2022 - Comments: 0

Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

Week In Review: Design, Low Power

By Jesse Allen - 17 Sep, 2021 - Comments: 0

MoSys, a provider of SRAM solutions and networking accelerators, and Peraso Technologies, a provider of 5G mmWave devices, are merging. Stockholders of Peraso are expected to hold a 61% equity interest in the combined company, with the remaining 39% equity interest to be retained by the stockholders of MoSys. Peraso CEO Ronald Glibbery said, "By joining with MoSys, we believe we can deliver a b... » read more

Manufacturing Bits: June 4

By Mark LaPedus - 04 Jun, 2019 - Comments: 0

Chiplet printer A number of companies, R&D organizations and universities separately presented a slew of papers and technologies at the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas. It’s difficult to write about all of the papers at ECTC. But one paper that stood out is a prototype chiplet micro-assembly printer developed by the Palo Alto Research Cente... » read more

Sorting Out Packaging Options

By Ed Sperling - 10 Sep, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Butler, executive vice president and general manager of SPTS Technologies; Ingu Yin Chang, senior vice president president at ASE Group; Hubert Karl Lakner, executive director of the Fraunhofer Institute for Photonic Microsystems; Robert Lo, division director for electronics and optoelectronics research at Industrial Te... » read more

The Week In Review: Design

By Jesse Allen - 10 Nov, 2017 - Comments: 0

IP Cryptographic flaws have been discovered in the IEEE P1735 standard for encrypting IP and managing access rights. A team from the University of Florida found "a surprising number of cryptographic mistakes in the standard. In the most egregious cases, these mistakes enable attack vectors that allow us to recover the entire underlying plaintext IP." The researchers warn that an adversary coul... » read more

What’s Next In Mobile Displays

By Mark LaPedus - 17 Dec, 2015 - Comments: 0

The next wave of smartphones and wearables is invading the market. These systems will feature a new class of high-resolution displays, and in the near future displays will become foldable and rollable, although there are still some challenges with this technology. To be sure, mobile display technology is advancing on several fronts. On one front, for example, Apple and other systems vendor... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Industrial Technology Research Institute

Study Of Bondable Laser Release Material Using 355nm Energy To Facilitate RDL-First And Die-First Fan-Out Wafer-Level Packaging (FOWLP)

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Manufacturing Bits: June 4

Sorting Out Packaging Options

The Week In Review: Design

What’s Next In Mobile Displays