Security Becoming Core Part Of Chip Design — Finally


Security is shifting both left and right in the design flow as chipmakers wrestle with how to build devices that are both secure by design and resilient enough to remain secure throughout their lifetimes. As increasingly complex devices are connected to the internet and to each other, IP vendors, chipmakers, and systems companies are racing to address existing and potential threats across a ... » read more

Auto Network Speeds Rise As Carmakers Prep For Autonomy


In-vehicle networks are starting to migrate from domain architectures to zonal architectures, an approach that will simplify and speed up communication in a vehicle using fewer protocols, less wiring, and ultimately lower cost. Zonal architectures will partition vehicles into zones that are more manageable and flexible, but getting there will take time. There is so much legacy technology in ... » read more

Overcoming The Challenges Of Capacitive Touch HMI Design


The capacitive touch human-machine interface (HMI) is a critical aspect of modern electronics. It is how we interact with our devices, making it an integral part of wearables, smart home products and IoT products. The primary goal of an HMI is to provide an intuitive and responsive interface that supports human interaction. However, designing a touch HMI system that meets the consumer's expecta... » read more

How To Meet The IoT Security Requirements Of Today And Tomorrow


Governments around the world are creating Internet of Things (IoT) security legislation and regulations designed to keep users safe in an increasingly connected world. Connectivity is good and, in fact, great but bad things can happen to people with unprotected or poorly protected IoT devices. Failing to meet government regulations or guidelines may lead to the inability to sell products in a r... » read more

Chip Industry Week In Review


By Susan Rambo, Gregory Haley, and Liz Allan Amkor plans to invest about $2 billion in a new advanced packaging and test facility in Peoria, Arizona. When finished, it will employ about 2,000 people and will be the largest outsourced advanced packaging facility in the U.S. The first phase of the construction is expected to be completed and operational within two to three years. Synopsys p... » read more

Chip Industry Week In Review


By Jesse Allen, Susan Rambo, and Liz Allan The U.S. government will invest about $3 billion for the National Advanced Packaging Manufacturing Program (NAPMP), including an advanced packaging piloting facility to help U.S. manufacturers adopt new technology and workforce training programs. It also will provide funding for projects concentrating on materials and substrates; equipment, tools, ... » read more

Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan Japan's Rapidus and the University of Tokyo are teaming up with France's Leti to meet its previously announced mass production goal of 2nm chips by 2027, and chips in the 1nm range in the 2030s. Rapidus was formed in 2022 with the support of eight Japanese companies — Sony, Kioxia, Denso, NEC, NTT, SoftBank, Toyota, and Mitsubishi's banking arm, ... » read more

Big Shifts In Power Electronics Packaging


The power semiconductor market is poised for remarkable growth in the next several years, fueled by the adoption of electric vehicles and renewable energy, but it also driving big changes in the packaging needed to protect and connect these devices. Packaging is playing an increasingly critical role in the transition to higher power densities, enabling more efficient power supplies, power deli... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan Bosch, Infineon, and NXP were cleared in Germany to each acquire 10% of the European Semiconductor Manufacturing Co. (ESMC), established by TSMC, solidifying the supply chain against future shortages, particularly for automotive chips. “ESMC intends to build and operate another large semiconductor factory in Dresden, in which the three Europ... » read more

Blog Review: Nov. 8


Siemens' Todd Westerhoff takes a look at the three stages of power integrity analysis for PCBs, challenges to board-level signal integrity, and best practices for getting the most accurate estimate of design performance. Synopsys' William Ruby provides a brief overview of the evolution of low-power design techniques and finds opportunities to reduce power and to make chip designs more energy... » read more

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